lemp10
Change-Id: Ia3d636931efd5bab6047a4305ba934b707043568
This commit is contained in:
Jeremy Soller
72
src/mainboard/system76/lemp10/Kconfig
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72
src/mainboard/system76/lemp10/Kconfig
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@@ -0,0 +1,72 @@
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if BOARD_SYSTEM76_LEMP10
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_PMC
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select EC_SYSTEM76_EC
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select EC_SYSTEM76_EC_BAT_THRESHOLDS
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_SMI_HANDLER
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select HAVE_SPD_IN_CBFS
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select PCIEXP_HOTPLUG
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select SOC_INTEL_TIGERLAKE
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select SOC_INTEL_COMMON_BLOCK_HDA
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM_RDRESP_NEED_DELAY
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select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
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config MAINBOARD_DIR
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string
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default "system76/lemp10"
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config MAINBOARD_PART_NUMBER
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string
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default "lemp10"
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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string
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default "Lemur Pro"
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config MAINBOARD_VERSION
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string
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default "lemp10"
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config CBFS_SIZE
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hex
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default 0xA00000
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config CONSOLE_POST
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bool
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default y
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config UART_FOR_CONSOLE
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int
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default 2
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config MAX_CPUS
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int
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default 8
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config DIMM_MAX
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int
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default 4 # Hack to make soc code work
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config DIMM_SPD_SIZE
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int
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default 512
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config POST_DEVICE
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bool
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default n
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endif
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2
src/mainboard/system76/lemp10/Kconfig.name
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2
src/mainboard/system76/lemp10/Kconfig.name
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@@ -0,0 +1,2 @@
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config BOARD_SYSTEM76_LEMP10
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bool "lemp10"
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4
src/mainboard/system76/lemp10/Makefile.inc
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4
src/mainboard/system76/lemp10/Makefile.inc
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@@ -0,0 +1,4 @@
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bootblock-y += bootblock.c
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ramstage-y += ramstage.c
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ramstage-y += hda_verb.c
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SPD_SOURCES = samsung-M471A1G44AB0-CWE
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30
src/mainboard/system76/lemp10/acpi/backlight.asl
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30
src/mainboard/system76/lemp10/acpi/backlight.asl
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@@ -0,0 +1,30 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <drivers/intel/gma/acpi/gma.asl>
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Scope (GFX0) {
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Name (BRIG, Package (22) {
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40, /* default AC */
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40, /* default Battery */
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5,
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10,
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15,
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20,
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25,
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30,
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35,
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40,
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45,
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50,
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55,
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60,
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65,
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70,
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75,
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80,
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85,
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90,
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95,
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100
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})
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}
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12
src/mainboard/system76/lemp10/acpi/mainboard.asl
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12
src/mainboard/system76/lemp10/acpi/mainboard.asl
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@@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define EC_GPE_SCI 0x6E
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#define EC_GPE_SWI 0x6B
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#include <ec/system76/ec/acpi/ec.asl>
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Scope (\_SB) {
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#include "sleep.asl"
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Scope (PCI0) {
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#include "backlight.asl"
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}
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}
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11
src/mainboard/system76/lemp10/acpi/sleep.asl
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11
src/mainboard/system76/lemp10/acpi/sleep.asl
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@@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Method called from _PTS prior to enter sleep state */
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Method (MPTS, 1) {
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\_SB.PCI0.LPCB.EC0.PTS (Arg0)
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}
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/* Method called from _WAK prior to wakeup */
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Method (MWAK, 1) {
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\_SB.PCI0.LPCB.EC0.WAK (Arg0)
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}
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8
src/mainboard/system76/lemp10/board_info.txt
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8
src/mainboard/system76/lemp10/board_info.txt
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@@ -0,0 +1,8 @@
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Vendor name: System76
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Board name: lemp10
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Category: laptop
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Release year: 2020
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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10
src/mainboard/system76/lemp10/bootblock.c
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10
src/mainboard/system76/lemp10/bootblock.c
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@@ -0,0 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <gpio.h>
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#include "gpio.h"
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void bootblock_mainboard_init(void)
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{
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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BIN
src/mainboard/system76/lemp10/data.vbt
Normal file
BIN
src/mainboard/system76/lemp10/data.vbt
Normal file
Binary file not shown.
305
src/mainboard/system76/lemp10/devicetree.cb
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305
src/mainboard/system76/lemp10/devicetree.cb
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@@ -0,0 +1,305 @@
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chip soc/intel/tigerlake
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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// Touchpad I2C bus
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# ACPI (soc/intel/tigerlake/acpi.c)
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# Disable DPTF
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register "dptf_enable" = "0"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# Disable s0ix
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register "s0ix_enable" = "0"
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# CPU (soc/intel/tigerlake/cpu.c)
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# Power limits
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register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
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// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
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.tdp_pl1_override = 28,
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// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
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.tdp_pl2_override = 46,
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}"
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register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
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// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
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.tdp_pl1_override = 28,
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// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
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.tdp_pl2_override = 46,
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}"
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# eSPI (soc/intel/tigerlake/espi.c)
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# LPC configuration from lspci -s 1f.0 -xxx
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# Address 0x84: Decode 0x80 - 0x8F (Port 80)
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register "gen1_dec" = "0x000c0081"
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# Address 0x88: Decode 0x68 - 0x6F (PMC)
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register "gen2_dec" = "0x00040069"
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# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
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register "gen3_dec" = "0x00fc0E01"
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# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
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register "gen4_dec" = "0x00fc0F01"
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# Finalize (soc/intel/tigerlake/finalize.c)
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# PM Timer Enabled
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register "PmTimerDisabled" = "0"
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# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
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# DDIA is eDP
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register "DdiPortAConfig" = "1"
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register "DdiPortAHpd" = "1"
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register "DdiPortADdc" = "0"
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# DDIB is HDMI
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register "DdiPortBConfig" = "0"
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register "DdiPortBHpd" = "1"
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register "DdiPortBDdc" = "1"
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# Enable C6 DRAM
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register "enable_c6dram" = "1"
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# High Definition Audio
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register "PchHdaAudioLinkHdaEnable" = "1"
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# System Agent dynamic frequency support
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register "SaGv" = "SaGv_Enabled"
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# TCSS USB3
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register "TcssXhciEn" = "1"
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# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
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# Enable DPTF device
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register "Device4Enable" = "1"
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#TODO: Hybrid storage mode
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register "HybridStorageMode" = "0"
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# SATA1 (SSD2)
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register "SataPortsEnable[1]" = "1"
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# I2C channels
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
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[PchSerialIoIndexI2C1] = PchSerialIoPci, // TODO: USB-PD?
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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}"
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# SPI channels
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
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}"
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#TODO: GSpiCsMode and GSpiCsState ?
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# UART channels
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoDisabled,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
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}"
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB Type-A Port 1 TODO
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C Port 2 TODO
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB Type-A Port 3 TODO
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C Port 4 TODO
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[7]" = "USB2_PORT_EMPTY"
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register "usb2_ports[8]" = "USB2_PORT_EMPTY"
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Port 1 TODO
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Port 2 TODO
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-A Port 3 TODO
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Type-C Port 4 TODO
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# PCIe root ports:
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# PCIe 4 x4 - SSD1
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# 3 x1 - WiFi
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# 6 x1 - CARD
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# 9 x4 - SSD2
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# PCIe clocks:
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# 0 - SSD1
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# 1 - WLAN
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# 2 - CARD
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# 3 - SSD2
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# PCIe PEG0 x4, Clock 0 (SSD1)
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register "PcieClkSrcUsage[0]" = "0x40"
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register "PcieClkSrcClkReq[0]" = "0"
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# PCIe root port #3 x1, Clock 1 (WLAN)
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register "PcieRpEnable[2]" = "1"
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register "PcieRpLtrEnable[2]" = "1"
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register "PcieClkSrcUsage[1]" = "2"
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register "PcieClkSrcClkReq[1]" = "1"
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||||
# PCIe root port #6 x1, Clock 2 (CARD)
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register "PcieRpEnable[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieClkSrcUsage[2]" = "5"
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register "PcieClkSrcClkReq[2]" = "2"
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||||
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||||
# PCIe root port #9 x4, Clock 3 (SSD2)
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register "PcieRpEnable[8]" = "1"
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||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[3]" = "8"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
|
||||
# Thermal
|
||||
# rdmsr --bitfield 31:24 --decimal 0x1A2
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||||
register "tcc_offset" = "8"
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||||
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||||
# Graphics (soc/intel/tigerlake/graphics.c)
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||||
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
|
||||
|
||||
# PMC (soc/intel/tigerlake/pmc.c)
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||||
# Disable deep Sx states
|
||||
register "deep_s3_enable_ac" = "0"
|
||||
register "deep_s3_enable_dc" = "0"
|
||||
register "deep_s5_enable_ac" = "0"
|
||||
register "deep_s5_enable_dc" = "0"
|
||||
register "deep_sx_config" = "0"
|
||||
|
||||
# PM Util (soc/intel/tigerlake/pmutil.c)
|
||||
# GPE configuration
|
||||
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
|
||||
register "pmc_gpe0_dw0" = "PMC_GPP_R"
|
||||
register "pmc_gpe0_dw1" = "PMC_GPP_B"
|
||||
register "pmc_gpe0_dw2" = "PMC_GPP_D"
|
||||
|
||||
# SMI Handler (soc/intel/tigerlake/smihandler.c)
|
||||
#TODO Disable HECI
|
||||
register "HeciEnabled" = "1"
|
||||
|
||||
# Actual device tree
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
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||||
|
||||
#TODO: Adjustments
|
||||
device domain 0 on
|
||||
#From EDS(575683)
|
||||
device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
|
||||
device pci 02.0 on end # Graphics
|
||||
device pci 04.0 on end # DPTF 0x9A03
|
||||
device pci 05.0 off end # IPU 0x9A19
|
||||
device pci 06.0 on end # PEG60 0x9A09
|
||||
device pci 07.0 on end # TBT_PCIe0 0x9A23
|
||||
device pci 07.1 off end # TBT_PCIe1 0x9A25
|
||||
device pci 07.2 off end # TBT_PCIe2 0x9A27
|
||||
device pci 07.3 off end # TBT_PCIe3 0x9A29
|
||||
device pci 08.0 off end # GNA 0x9A11
|
||||
device pci 09.0 off end # NPK 0x9A33
|
||||
device pci 0a.0 on end # Crash-log SRAM 0x9A0D
|
||||
device pci 0d.0 on end # USB xHCI 0x9A13
|
||||
device pci 0d.1 off end # USB xDCI (OTG) 0x9A15
|
||||
device pci 0d.2 on end # TBT DMA0 0x9A1B
|
||||
device pci 0d.3 off end # TBT DMA1 0x9A1D
|
||||
device pci 0e.0 off end # VMD 0x9A0B
|
||||
|
||||
# From PCH EDS(576591)
|
||||
device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
|
||||
device pci 10.6 off end # THC0 0xA0D0
|
||||
device pci 10.7 off end # THC1 0xA0D1
|
||||
device pci 12.0 off end # SensorHUB 0xA0FC
|
||||
device pci 12.6 off end # GSPI2 0x34FB
|
||||
device pci 13.0 off end # GSPI3 0xA0FD
|
||||
device pci 14.0 on end # USB3.1 xHCI 0xA0ED
|
||||
device pci 14.1 off end # USB3.1 xDCI 0xA0EE
|
||||
device pci 14.2 on end # Shared RAM 0xA0EF
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
|
||||
end
|
||||
|
||||
device pci 15.0 on # I2C0 0xA0E8
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""ELAN Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)"
|
||||
register "generic.probed" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
end # I2C0
|
||||
device pci 15.1 on end # I2C1 0xA0E9
|
||||
device pci 15.2 off end # I2C2 0xA0EA
|
||||
device pci 15.3 off end # I2C3 0xA0EB
|
||||
device pci 16.0 on end # HECI1 0xA0E0
|
||||
device pci 16.1 off end # HECI2 0xA0E1
|
||||
device pci 16.2 off end # CSME 0xA0E2
|
||||
device pci 16.3 off end # CSME 0xA0E3
|
||||
device pci 16.4 off end # HECI3 0xA0E4
|
||||
device pci 16.5 off end # HECI4 0xA0E5
|
||||
device pci 17.0 on end # SATA 0xA0D3
|
||||
device pci 19.0 off end # I2C4 0xA0C5
|
||||
device pci 19.1 off end # I2C5 0xA0C6
|
||||
device pci 19.2 on end # UART2 0xA0C7
|
||||
device pci 1c.0 off end # RP1 0xA0B8
|
||||
device pci 1c.1 off end # RP2 0xA0B9
|
||||
device pci 1c.2 on end # RP3 0xA0BA
|
||||
device pci 1c.3 off end # RP4 0xA0BB
|
||||
device pci 1c.4 off end # RP5 0xA0BC
|
||||
device pci 1c.5 on end # RP6 0xA0BD
|
||||
device pci 1c.6 off end # RP7 0xA0BE
|
||||
device pci 1c.7 off end # RP8 0xA0BF
|
||||
device pci 1d.0 on end # RP9 0xA0B0
|
||||
device pci 1d.1 off end # RP10 0xA0B1
|
||||
device pci 1d.2 off end # RP11 0xA0B2
|
||||
device pci 1d.3 off end # RP12 0xA0B3
|
||||
device pci 1e.0 off end # UART0 0xA0A8
|
||||
device pci 1e.1 off end # UART1 0xA0A9
|
||||
device pci 1e.2 off end # GSPI0 0xA0AA
|
||||
device pci 1e.3 off end # GSPI1 0xA0AB
|
||||
device pci 1f.0 on # eSPI 0xA080 - A09F
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # P2SB 0xA0A0
|
||||
device pci 1f.2 hidden # PMC 0xA0A1
|
||||
# TODO: verify
|
||||
# The pmc_mux chip driver is a placeholder for the
|
||||
# PMC.MUX device in the ACPI hierarchy.
|
||||
# chip drivers/intel/pmc_mux
|
||||
# device generic 0 on
|
||||
# chip drivers/intel/pmc_mux/conn
|
||||
# register "usb2_port_number" = "2"
|
||||
# register "usb3_port_number" = "2"
|
||||
# # SBU is fixed, HSL follows CC
|
||||
# register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||
# device generic 0 on end
|
||||
# end
|
||||
# chip drivers/intel/pmc_mux/conn
|
||||
# register "usb2_port_number" = "6"
|
||||
# register "usb3_port_number" = "4"
|
||||
# # SBU is fixed, HSL follows CC
|
||||
# register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
|
||||
# device generic 1 on end
|
||||
# end
|
||||
# end
|
||||
# end
|
||||
end # PMC
|
||||
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
|
||||
device pci 1f.4 on end # SMBus 0xA0A3
|
||||
device pci 1f.5 on end # SPI 0xA0A4
|
||||
device pci 1f.6 off end # GbE 0x15E1/0x15E2
|
||||
device pci 1f.7 off end # TH 0xA0A6
|
||||
end
|
||||
end
|
||||
33
src/mainboard/system76/lemp10/dsdt.asl
Normal file
33
src/mainboard/system76/lemp10/dsdt.asl
Normal file
@@ -0,0 +1,33 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
//TODO: cleaner solution for ACPI brightness
|
||||
#define SYSTEM76_ACPI_NO_GFX0
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0 and up
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0) {
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/southbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/tcss.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB.PCI0.LPCB) {
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
221
src/mainboard/system76/lemp10/gpio.h
Normal file
221
src/mainboard/system76/lemp10/gpio.h
Normal file
@@ -0,0 +1,221 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
};
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD2, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD7, 1, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
PAD_CFG_TERM_GPO(GPD9, 0, NONE, PWROK),
|
||||
PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3),
|
||||
PAD_NC(GPP_A10, NONE),
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_A13, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
PAD_NC(GPP_A15, NONE),
|
||||
PAD_NC(GPP_A16, NONE),
|
||||
PAD_NC(GPP_A17, NONE),
|
||||
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_A19, NONE),
|
||||
PAD_NC(GPP_A20, NONE),
|
||||
PAD_NC(GPP_A21, NONE),
|
||||
PAD_NC(GPP_A22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_A23, 0, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B2, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B3, 0x80800100, 0x0000),
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_NC(GPP_B7, NONE),
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B14, 0, NONE, DEEP),
|
||||
PAD_NC(GPP_B15, NONE),
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_NC(GPP_B18, NONE),
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_NC(GPP_B22, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_B23, 0, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_C2, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C5, NONE),
|
||||
PAD_CFG_NF(GPP_C6, NONE, PWROK, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, PWROK, NF1),
|
||||
PAD_NC(GPP_C8, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_C9, 0x40100100, 0x3000),
|
||||
PAD_NC(GPP_C10, NONE),
|
||||
PAD_NC(GPP_C11, NONE),
|
||||
PAD_NC(GPP_C12, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_C13, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_C14, DN_20K),
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_C20, NONE),
|
||||
PAD_NC(GPP_C21, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
|
||||
_PAD_CFG_STRUCT(GPP_C23, 0x40880100, 0x0000),
|
||||
PAD_CFG_TERM_GPO(GPP_D0, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, DN_20K, DEEP),
|
||||
PAD_NC(GPP_D4, NONE),
|
||||
// SSD1_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
|
||||
// WLAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
|
||||
// CARD_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
|
||||
// SSD2_CLKREQ#
|
||||
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_D9, 0x84001601, 0x0000),
|
||||
PAD_NC(GPP_D10, NONE),
|
||||
PAD_CFG_GPI(GPP_D11, DN_20K, DEEP),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_D14, 1, NONE, PLTRST),
|
||||
PAD_NC(GPP_D15, NONE),
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_CFG_GPI(GPP_D17, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_D18, NONE, DEEP),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
PAD_CFG_TERM_GPO(GPP_E1, 0, NONE, PLTRST),
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
PAD_CFG_GPI(GPP_E3, DN_20K, DEEP),
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_NC(GPP_E5, NONE),
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
PAD_NC(GPP_E8, NONE),
|
||||
PAD_NC(GPP_E9, NONE),
|
||||
PAD_NC(GPP_E10, NONE),
|
||||
PAD_NC(GPP_E11, NONE),
|
||||
PAD_NC(GPP_E12, NONE),
|
||||
PAD_NC(GPP_E13, NONE),
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_E15, DN_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000),
|
||||
PAD_NC(GPP_E17, NONE),
|
||||
_PAD_CFG_STRUCT(GPP_E18, 0x44001700, 0x3c00),
|
||||
_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
|
||||
_PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000),
|
||||
PAD_NC(GPP_E21, NONE),
|
||||
PAD_NC(GPP_E22, NONE),
|
||||
PAD_NC(GPP_E23, NONE),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
|
||||
PAD_NC(GPP_F4, NONE),
|
||||
PAD_NC(GPP_F5, NONE),
|
||||
PAD_NC(GPP_F6, NONE),
|
||||
PAD_NC(GPP_F7, NONE),
|
||||
PAD_NC(GPP_F8, NONE),
|
||||
PAD_NC(GPP_F9, NONE),
|
||||
PAD_NC(GPP_F10, NONE),
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_NC(GPP_F15, NONE),
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPI(GPP_F17, NONE, PLTRST),
|
||||
PAD_NC(GPP_F18, NONE),
|
||||
PAD_NC(GPP_F19, NONE),
|
||||
PAD_NC(GPP_F20, NONE),
|
||||
PAD_CFG_GPI(GPP_F21, DN_20K, DEEP),
|
||||
PAD_NC(GPP_F22, NONE),
|
||||
PAD_NC(GPP_F23, NONE),
|
||||
PAD_NC(GPP_H0, DN_20K),
|
||||
PAD_NC(GPP_H1, DN_20K),
|
||||
PAD_NC(GPP_H2, DN_20K),
|
||||
PAD_CFG_GPI(GPP_H3, DN_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP),
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_CFG_GPI(GPP_H8, DN_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H9, DN_20K, DEEP),
|
||||
PAD_NC(GPP_H10, NONE),
|
||||
PAD_NC(GPP_H11, NONE),
|
||||
PAD_NC(GPP_H12, NONE),
|
||||
PAD_NC(GPP_H13, NONE),
|
||||
PAD_NC(GPP_H14, NONE),
|
||||
PAD_NC(GPP_H15, NONE),
|
||||
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_NC(GPP_H23, NONE),
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP),
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
PAD_NC(GPP_U4, NONE),
|
||||
PAD_NC(GPP_U5, NONE),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
26
src/mainboard/system76/lemp10/hda_verb.c
Normal file
26
src/mainboard/system76/lemp10/hda_verb.c
Normal file
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC293 */
|
||||
0x10ec0293, /* Vendor ID */
|
||||
0x155814a1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155814a1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x02211020),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x41748245),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
8
src/mainboard/system76/lemp10/ramstage.c
Normal file
8
src/mainboard/system76/lemp10/ramstage.c
Normal file
@@ -0,0 +1,8 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
31
src/mainboard/system76/lemp10/romstage.c
Normal file
31
src/mainboard/system76/lemp10/romstage.c
Normal file
@@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/util.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_ddr4_cfg board_cfg = {
|
||||
// dq_map unused on DDR4
|
||||
// dqs_map unused on DDR4
|
||||
|
||||
// TGL-U does not support interleaved memory
|
||||
.dq_pins_interleaved = 0,
|
||||
|
||||
//TODO: can we use early command training?
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
static const struct spd_info spd = {
|
||||
.topology = MIXED,
|
||||
.md_spd_loc = SPD_CBFS,
|
||||
.cbfs_index = 0,
|
||||
.smbus_info[1] = {
|
||||
.addr_dimm0 = 0x52,
|
||||
},
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd) {
|
||||
//TODO: what is this for?
|
||||
const bool half_populated = false;
|
||||
meminit_ddr4(&mupd->FspmConfig, &board_cfg, &spd, half_populated);
|
||||
}
|
||||
@@ -0,0 +1,33 @@
|
||||
# Samsung M471A1G44AB0-CWE
|
||||
23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5
|
||||
0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 47
|
||||
34 34 41 42 30 2D 43 57 45 20 20 20 20 00 80 CE
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
Reference in New Issue
Block a user