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nb/intel/sandybridge: Use new fixed BAR accessors

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One instance in northbridge.c breaks reproduciblity when changed.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.

Change-Id: I2148183827bcacc9e6edb91b26ad35eb2dae5090
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51866
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-03-26 13:33:22 +01:00
committed by Nico Huber
parent 2e397aebad
commit 66780a0c9f
12 changed files with 320 additions and 336 deletions
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8
src/northbridge/intel/sandybridge/raminit.c
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@ -300,7 +300,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
timestamp_add_now(TS_BEFORE_INITRAM);
MCHBAR32(SAPMCTL) |= 1;
mchbar_setbits32(SAPMCTL, 1 << 0);
/* Wait for ME to be ready */
intel_early_me_init();
@ -312,9 +312,9 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
wrmsr(0x2e6, (msr_t) { .lo = 0, .hi = 0 });
const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000
const u32 sskpd = mchbar_read32(SSKPD); // !!! = 0x00000000
if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) {
MCHBAR32(SSKPD) = 0;
mchbar_write32(SSKPD, 0);
/* Need reset */
system_reset();
}
@ -413,7 +413,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
die("raminit failed");
/* FIXME: should be hardware revision-dependent. The register only exists on IVB. */
MCHBAR32(CHANNEL_HASH) = 0x00a030ce;
mchbar_write32(CHANNEL_HASH, 0x00a030ce);
set_scrambling_seed(&ctrl);