ACPI: Refactor ChromeOS specific ACPI GNVS

The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.

If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.

If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.

Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.

Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/baytrail/include/soc/nvs.h

@@ -4,8 +4,6 @@
 #define _BAYTRAIL_NVS_H_
 
 #include <stdint.h>
-#include <commonlib/helpers.h>
-#include <vendorcode/google/chromeos/gnvs.h>
 #include <soc/device_nvs.h>
 
 struct __packed global_nvs {
@@ -50,12 +48,10 @@ struct __packed global_nvs {
 	u8	unused[76];
 
 	/* ChromeOS specific (0x100-0xfff) */
-	chromeos_acpi_t chromeos;
+	u8	chromeos_reserve[0xf00];
 
 	/* Baytrail LPSS (0x1000) */
 	device_nvs_t dev;
 };
 
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
 #endif /* _BAYTRAIL_NVS_H_ */