sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Documentation: x86 Enable Serial Output

Browse Source 
Document the steps necessary to enable serial output

TEST=None

Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13444
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
2016-02-04 11:21:33 -08:00
committed by Leroy P Leahy
parent 7e0078b990
commit 66decf1644
4 changed files with 111 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
Documentation/Intel/development.html
View File

@@ -71,6 +71,17 @@
<li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
<li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
<li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li>
<li>Enable the serial port
<ol type="A">
<li>Power on, enable and configure GPIOs for the
<a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a>
</li>
<li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a>
support to romstage
</li>
</ol>
</li>
<li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li>
</ol>
@@ -106,6 +117,23 @@
Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
</td>
</tr>
<tr bgcolor="#c0ffc0">
<th>Board</th>
<th>Where</th>
<th>Testing</th>
</tr>
<tr>
<td>Serial Port</td>
<td>
SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br>
Enable: src/soc/mainboard/&lt;Board&gt;/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a>
</td>
<td>Debug serial output works</td>
</tr>
<tr bgcolor="#c0ffc0">
<th>FSP</th>
<th>Where</th>