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soc/amd/stoneyridge: use SoC common uart ops

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Define the UARTs as MMIO devices in the chipset devicetrees. Drop ACPI
_STA in asl since now handled by common SSDT generator. Implement
wait_for_aoac_enabled() since required by SoC common code, and ensure
compiled during all stages necessary.

TEST=build/boot google/liara, verify console UART still functional.

Change-Id: Ibecafdfa189d9c63a29b63759c5b965d03719009
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77093
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier
2023-08-08 12:28:03 -05:00
committed by Felix Held
parent d59c79987d
commit 66ff4fb1a5
5 changed files with 11 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/amd/stoneyridge/Makefile.inc
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@@ -28,6 +28,7 @@ verstage-y += i2c.c
postcar-y += memmap.c postcar-y += memmap.c
postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
ramstage-y += aoac.c
ramstage-y += BiosCallOuts.c ramstage-y += BiosCallOuts.c
ramstage-y += i2c.c ramstage-y += i2c.c
ramstage-y += chip.c ramstage-y += chip.c

8
src/soc/amd/stoneyridge/acpi/mmio.asl
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@@ -47,10 +47,6 @@ Device (FUR0)
IRQ (Edge, ActiveHigh, Exclusive) { 10 } IRQ (Edge, ActiveHigh, Exclusive) { 10 }
Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x2000) Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x2000)
}) })
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
}
} }
Device (FUR1) { Device (FUR1) {
@@ -61,10 +57,6 @@ Device (FUR1) {
IRQ (Edge, ActiveHigh, Exclusive) { 11 } IRQ (Edge, ActiveHigh, Exclusive) { 11 }
Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x2000) Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x2000)
}) })
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
}
} }
Device (I2CA) { Device (I2CA) {

6
src/soc/amd/stoneyridge/aoac.c
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@@ -21,6 +21,12 @@ static const unsigned int aoac_devs[] = {
FCH_AOAC_DEV_I2C3, FCH_AOAC_DEV_I2C3,
}; };
void wait_for_aoac_enabled(unsigned int dev)
{
while (!is_aoac_device_enabled(dev))
udelay(100);
}
void enable_aoac_devices(void) void enable_aoac_devices(void)
{ {
bool status; bool status;

2
src/soc/amd/stoneyridge/chipset_cz.cb
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@@ -43,4 +43,6 @@ chip soc/amd/stoneyridge
device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc6000 alias uart_0 off ops amd_uart_mmio_ops end
device mmio 0xfedc8000 alias uart_1 off ops amd_uart_mmio_ops end
end end

2
src/soc/amd/stoneyridge/chipset_st.cb
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@@ -37,4 +37,6 @@ chip soc/amd/stoneyridge
device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
device mmio 0xfedc6000 alias uart_0 off ops amd_uart_mmio_ops end
device mmio 0xfedc8000 alias uart_1 off ops amd_uart_mmio_ops end
end end