From 6734cf0eefe1e7ea7031c87d9e09196661d11a0a Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Fri, 30 Dec 2022 14:18:18 -0700 Subject: [PATCH] mb/system76/adl-p: galp6: Enable AER on CPU PCIe RP Change-Id: Ia9cb20a73bfc2bc8b856dbcf16d632c8640cc4bb Signed-off-by: Tim Crawford --- src/mainboard/system76/adl-p/variants/galp6/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb index e63e185c1f..c10e17adbc 100644 --- a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb @@ -18,7 +18,7 @@ chip soc/intel/alderlake register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_src = 0, .clk_req = 0, - .flags = PCIE_RP_LTR, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN