nb/intel/ironlake: Add SAD DRAM register definitions

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/ironlake/ironlake.h

@@ -57,6 +57,9 @@
 
 #define SAD_PCIEXBAR		0x50
 
+#define SAD_DRAM_RULE(x)	(0x80 + 4 * (x)) /* 0-7 */
+#define SAD_INTERLEAVE_LIST(x)	(0xc0 + 4 * (x)) /* 0-7 */
+
 
 /* Device 0:2.0 PCI configuration space (Graphics Device) */