arch/x86: Fix S3 resume without stage cache

It was possible to have NO_STAGE_CACHE=n and at the same time have
TSEG_STAGE_CACHE=n and CBMEM_STAGE_CACHE=n. This resulted with a
failing attempt to load STAGE_POSTCAR from the stage cache, but not
loading it from CBFS either.

Make it a three-way choice between different STAGE_CACHE options.
For AGESA disable CBMEM_STAGE_CACHE by default, as it is no longer
needed to have functional ACPI S3 resume and it is not allowed
se use keyword select for symbols inside choice blocks.

Change-Id: I0da3e1cf4c92817ffabbb02eda3476ecdfdfa278
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37683
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/amd/agesa/Kconfig

@@ -26,7 +26,6 @@ config CPU_AMD_AGESA
 	select UDELAY_LAPIC
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
-	select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME
 	select SMM_ASEG
 	select NO_FIXED_XIP_ROM_SIZE
 	select SSE2