This patch makes several CMOS/NVRAM reads dependent on whether there's a table to read. Otherwise you never know what you'll get from the factory BIOS. There are probably more, but these are the ones compiled into the s2895.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -598,11 +598,11 @@ static void hw_enable_ecc(const struct mem_controller *ctrl)
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if (nbcap & NBCAP_ECC) {
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dcl |= DCL_DimmEccEn;
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}
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if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
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if (HAVE_OPTION_TABLE &&
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read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
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dcl &= ~DCL_DimmEccEn;
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}
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pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
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}
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static int is_dual_channel(const struct mem_controller *ctrl)
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@@ -1146,7 +1146,8 @@ static void order_dimms(const struct mem_controller *ctrl)
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{
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unsigned long tom_k, base_k;
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if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
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if ((!HAVE_OPTION_TABLE) ||
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read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
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tom_k = interleave_chip_selects(ctrl);
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} else {
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print_debug("Interleaving disabled\r\n");
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@@ -1450,7 +1451,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
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min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
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bios_cycle_time = min_cycle_times[
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read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
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if (bios_cycle_time > min_cycle_time) {
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if (HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) {
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min_cycle_time = bios_cycle_time;
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}
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min_latency = 2;
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