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libpayload arm64: Remove tight-coupling with any particular EL

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Allow more flexibility by reading and writing to system registers at current
EL. Instead of specifying what _ELx register to write to, code can specify
_current.

BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles and boots to kernel on ryu

Change-Id: Id38b675bfe67ca1e25f8c268192114e3f0bee800
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6d4d07e26fc964dc3aaebfe03db59596d90093e9
Original-Change-Id: Ic1d9e18e6fc016a04f17621a148e62d6cbd04ce7
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214577
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8785
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh
2014-08-27 16:00:24 -07:00
committed by Patrick Georgi
parent 635b45d608
commit 678dee08f6
2 changed files with 13 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
payloads/libpayload/arch/arm64/cache.c
View File

@ -39,7 +39,7 @@
void tlb_invalidate_all(void) void tlb_invalidate_all(void)
{ {
/* TLBIALL includes dTLB and iTLB on systems that have them. */ /* TLBIALL includes dTLB and iTLB on systems that have them. */
tlbiall_el3(); tlbiall_current();
dsb(); dsb();
isb(); isb();
} }
@ -127,18 +127,18 @@ void dcache_mmu_disable(void)
uint32_t sctlr; uint32_t sctlr;
dcache_clean_invalidate_all(); dcache_clean_invalidate_all();
sctlr = raw_read_sctlr_el3(); sctlr = raw_read_sctlr_current();
sctlr &= ~(SCTLR_C | SCTLR_M); sctlr &= ~(SCTLR_C | SCTLR_M);
raw_write_sctlr_el3(sctlr); raw_write_sctlr_current(sctlr);
} }
void dcache_mmu_enable(void) void dcache_mmu_enable(void)
{ {
uint32_t sctlr; uint32_t sctlr;
sctlr = raw_read_sctlr_el3(); sctlr = raw_read_sctlr_current();
sctlr |= SCTLR_C | SCTLR_M; sctlr |= SCTLR_C | SCTLR_M;
raw_write_sctlr_el3(sctlr); raw_write_sctlr_current(sctlr);
} }
void cache_sync_instructions(void) void cache_sync_instructions(void)

15
payloads/libpayload/arch/arm64/exception_asm.S
View File

@ -27,6 +27,9 @@
* SUCH DAMAGE. * SUCH DAMAGE.
*/ */
#define __ASSEMBLY__
#include <arch/lib_helpers.h>
.text .text
/* Macro for exception entry /* Macro for exception entry
@ -89,10 +92,10 @@ exception_prologue:
stp x0, x1, [sp, #-16]! stp x0, x1, [sp, #-16]!
/* Save the exception reason on stack */ /* Save the exception reason on stack */
mrs x1, esr_el3 read_current x1, esr
/* Save the return address on stack */ /* Save the return address on stack */
mrs x0, elr_el3 read_current x0, elr
stp x0, x1, [sp, #-16]! stp x0, x1, [sp, #-16]!
ret ret
@ -106,8 +109,8 @@ exception_handler:
/* Pop return address saved on stack */ /* Pop return address saved on stack */
ldp x0, x1, [sp], #16 ldp x0, x1, [sp], #16
msr elr_el3, x0 write_current elr, x0, x2
msr esr_el3, x1 write_current esr, x1, x2
/* Pop exception reason saved on stack, followed by regs x0-x30 */ /* Pop exception reason saved on stack, followed by regs x0-x30 */
ldp x0, x1, [sp], #16 ldp x0, x1, [sp], #16
ldp x2, x3, [sp], #16 ldp x2, x3, [sp], #16
@ -129,7 +132,5 @@ exception_handler:
.global set_vbar .global set_vbar
set_vbar: set_vbar:
/* Initialize the exception table address in vbar for EL3 */ write_current vbar, x0, x1
/* FIXME: Do we need to initialize for other levels too? EL1/EL2 */
msr vbar_el3, x0
ret ret