From 67a59cb124c3b93f6f60d17fbeb9e44eb1311604 Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Wed, 22 Jun 2022 09:09:50 -0600
Subject: [PATCH] mb/system76/adl-p: Add Lemur Pro 11 as a variant

Change-Id: Ib17041a891917cd4659004aba6a9a55b591865ae
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 src/mainboard/system76/adl-p/Kconfig          |   7 +-
 src/mainboard/system76/adl-p/Kconfig.name     |   3 +
 src/mainboard/system76/adl-p/Makefile.inc     |   2 +
 .../spd/samsung-P4AAF165WA-BCWDE.spd.hex      |  33 +++
 .../adl-p/variants/lemp11/board_info.txt      |   2 +
 .../system76/adl-p/variants/lemp11/data.vbt   | Bin 0 -> 8704 bytes
 .../system76/adl-p/variants/lemp11/gpio.c     | 227 ++++++++++++++++++
 .../adl-p/variants/lemp11/gpio_early.c        |  14 ++
 .../system76/adl-p/variants/lemp11/hda_verb.c |  25 ++
 .../adl-p/variants/lemp11/overridetree.cb     | 167 +++++++++++++
 .../system76/adl-p/variants/lemp11/romstage.c |  24 ++
 11 files changed, 503 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/system76/adl-p/spd/samsung-P4AAF165WA-BCWDE.spd.hex
 create mode 100644 src/mainboard/system76/adl-p/variants/lemp11/board_info.txt
 create mode 100644 src/mainboard/system76/adl-p/variants/lemp11/data.vbt
 create mode 100644 src/mainboard/system76/adl-p/variants/lemp11/gpio.c
 create mode 100644 src/mainboard/system76/adl-p/variants/lemp11/gpio_early.c
 create mode 100644 src/mainboard/system76/adl-p/variants/lemp11/hda_verb.c
 create mode 100644 src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb
 create mode 100644 src/mainboard/system76/adl-p/variants/lemp11/romstage.c

diff --git a/src/mainboard/system76/adl-p/Kconfig b/src/mainboard/system76/adl-p/Kconfig
index 942c7350f3..f0e1e5a2bc 100644
--- a/src/mainboard/system76/adl-p/Kconfig
+++ b/src/mainboard/system76/adl-p/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_SYSTEM76_DARP8
+if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_LEMP11
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
 	select HAVE_OPTION_TABLE
+	select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP11
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_LPSS_UART_FOR_CONSOLE
 	select MAINBOARD_HAS_TPM2
@@ -30,18 +31,22 @@ config MAINBOARD_DIR
 
 config VARIANT_DIR
 	default "darp8" if BOARD_SYSTEM76_DARP8
+	default "lemp11" if BOARD_SYSTEM76_LEMP11
 
 config OVERRIDE_DEVICETREE
 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config MAINBOARD_PART_NUMBER
 	default "darp8" if BOARD_SYSTEM76_DARP8
+	default "lemp11" if BOARD_SYSTEM76_LEMP11
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "Darter Pro" if BOARD_SYSTEM76_DARP8
+	default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
 
 config MAINBOARD_VERSION
 	default "darp8" if BOARD_SYSTEM76_DARP8
+	default "lemp11" if BOARD_SYSTEM76_LEMP11
 
 config CBFS_SIZE
 	default 0xA00000
diff --git a/src/mainboard/system76/adl-p/Kconfig.name b/src/mainboard/system76/adl-p/Kconfig.name
index 9533451123..3fe235f7ee 100644
--- a/src/mainboard/system76/adl-p/Kconfig.name
+++ b/src/mainboard/system76/adl-p/Kconfig.name
@@ -1,2 +1,5 @@
 config BOARD_SYSTEM76_DARP8
 	bool "darp8"
+
+config BOARD_SYSTEM76_LEMP11
+	bool "lemp11"
diff --git a/src/mainboard/system76/adl-p/Makefile.inc b/src/mainboard/system76/adl-p/Makefile.inc
index 8989d5ce6e..f3dc7e107b 100644
--- a/src/mainboard/system76/adl-p/Makefile.inc
+++ b/src/mainboard/system76/adl-p/Makefile.inc
@@ -8,3 +8,5 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+
+SPD_SOURCES = samsung-P4AAF165WA-BCWDE
diff --git a/src/mainboard/system76/adl-p/spd/samsung-P4AAF165WA-BCWDE.spd.hex b/src/mainboard/system76/adl-p/spd/samsung-P4AAF165WA-BCWDE.spd.hex
new file mode 100644
index 0000000000..28e4a613c2
--- /dev/null
+++ b/src/mainboard/system76/adl-p/spd/samsung-P4AAF165WA-BCWDE.spd.hex
@@ -0,0 +1,33 @@
+# Samsung P4AAF165WA-BCWDE
+23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E 30 11
+F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
+16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 DE DE
+0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+80 CE 00 00 00 00 00 00 00 50 34 41 41 46 31 36
+35 57 41 2D 42 43 57 44 45 20 20 20 20 00 80 CE
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/system76/adl-p/variants/lemp11/board_info.txt b/src/mainboard/system76/adl-p/variants/lemp11/board_info.txt
new file mode 100644
index 0000000000..301c2d3aa6
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/lemp11/board_info.txt
@@ -0,0 +1,2 @@
+Board name: lemp11
+Release year: 2022
diff --git a/src/mainboard/system76/adl-p/variants/lemp11/data.vbt b/src/mainboard/system76/adl-p/variants/lemp11/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..3d822c3942b023bc031261f86f734306f2232b1e
GIT binary patch
literal 8704
zcmeHMUrbw782`?_ZRu)}PRQ2bh6lDVK>l3HhK!KxmVd4re_CMJWhNBX>d4q&j2Sd0
z)Px6&F}aC}VT;Db#Hc*svoC#_l4xSH2cwA(B)%+*zVYD0X8oOWFNJQf)y3(U{hIII
zbI<oXzx#dPIrrRiPY(^Z4{?7_XV*ZF|5R69kVB%R(cSV|9PgL*K>y%Kr+>&l(%#eG
zaf<&zd+7V}KW`I78QbS>)U?LHrJ2}7)j&1xog5pVh&6P^u3VUzoZ`Wb0Qa9e7n_Jp
zkIuxRd~o<>KNoz3uJ)_r6H(rG_2O7;x|M@O1DZD;sc$;Mx$mV0t*ODMH6DefwXwPN
z=&?dqXIDpmZ!pl~9}4vM@%{nc85r~r4tDjn_nhIuf&LSL_P|hAXQ3-AgpSFnH>by6
zKR?5(I;y!3_o<V-(q-N;IXzX+{Sy;>Kwz%$f!LMU^c%5geW6PbCCO=HM9e`&I1=4$
zCl5JsgE-U%)u9~ffhtg7tb-_QEy{aLLEFPla(Fi*a6c8-Ns#hPJ(su2T%xeoyh!4n
zJX6o%&CLj%J!?BqE_@*>FdYJnap{$b)#;n_<nhok3s$&((})EVE{K>+*l7!f@I|;u
zn#zKCEZAiWwwuT<Veu@OV!__GV8uiZ2{W=_(oOjGr3FI>LXt!lOk6<(4zL>*OxA6N
z$q<CQxyYTjfU*+AhzTLu&Gh@)eygtBSNDqDMWfIQ(5uin=)2GlpdUj&hkgb98hQiz
z1N3L;uh8G2yP}{}<j8qk$0dmCJIXv2>GXOOJGJC4rjr<rs<Ul=zl`NHQTmgTC32XT
zL~ZLKZgGAhY|q!KsR9?J3f9;{@sm|rV|Sbj#S3^ubCt|EGAEu~n{9!+rQR~9pDk?p
zs{d~Wsw${RZOV#YOlv|mDr<)Aab=aocRwp%Y0hakp0BXtmghC*!P#DPn9}JVcf}39
zdcfn1RG6*Hn&&X{i?W-mVddcri6Tyo;r+ZSUXo!j=WlY0nd#vS(S4-*sZ#SUG@A_G
z<~dcq{=r};n_y_ev#@;>S`96RNYk|`>rq7%Xeij+v-Z-Q7-o5>)T4VgF)%~CzjI~y
zqG5J5R9dNr7dL!hhIqA;TX!ty;KPaIx;D1#)Ai&AgF~!cz%XpjC6lj}4=;tNOzSqR
zz7Ux-#2Ss@N-lYLyWU7dO3QSOTYZ5{+KgS&hj>9QQB<|X6I06v!B8Vw5sAJq<SW;m
zu+Qf(9<Em>Qla?@EqKjZ-hn}-X9O2AnG1tfqpw8fqnbBlt$ZYdTQWT2n3N1yAi@W-
z^BkhMT}p`{->bQ`4$(^HK{fC^f+1eeBFBRm<lB#Gr8Vxo+)}59>o)pA6^n1-0~X8=
ze=e$Zio~fn;_+ZHDnv#hUrp|w?%+sp^ipi1Z}ej9DY!5Le7whW`o%`(IJrWO@X}*B
z8Vt<odqh!`=b#x8i`GZgAliyK=}}dTKIc7xss~DKAN|%1L;wr#(-fpA)v^x>s~f~Q
zCw>TLPQ<+D9zlI(fxh_;^%|pvjO>h}>Hm5-|N6N}PT{5#N18G17?=g*gt$4eD5ulM
zW!A;iE4)luAD&_&Et-4bcnLaDbmn%_)<#a>cx87pql4p@eE3WpscIu1;PPV<=lq>F
za+lBcKR?3OnE6{M{`;kkp2;pbq_o^5xdO<x?eME(11^VLTkY^T^6uv|kk3Fq1NjW(
zGmy_fJ_Gp-{D&E6{Z!dcuZ|JL6$4vU5n5#jtpE1ppOd72g#T4lVpSBUFtE(rt)(QK
zzI7J|o6fwnfZgj#Y?6uH3UEPJKf~U%eUWK21&oGv_?Cqvp~5z6=gb3Jsm+sRGky`a
zRTid2*ebJZsab_|ho<OYS+@DIY<GGY4cnJkHyQAy3^ws0Z2Iz3ijm<+kVYJwWf?z{
zup4I-iWiu+W!pi-ZvN>gY_<fWggwQAbdBcK3UHd=*uo}a&>bt}r4VdUfrgs#ZI_oM
z?1u_PUK04Ehd1h8wA#o^NvH6|i`eU^#a5T)=k<3KZ0JPr|2g&p9L4ZO?)}SrKB)hm
I1{>1$7pzZr3IG5A

literal 0
HcmV?d00001

diff --git a/src/mainboard/system76/adl-p/variants/lemp11/gpio.c b/src/mainboard/system76/adl-p/variants/lemp11/gpio.c
new file mode 100644
index 0000000000..fb49ac76d8
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/lemp11/gpio.c
@@ -0,0 +1,227 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_NC(GPD2, NONE),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
+	PAD_NC(GPD11, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
+	PAD_NC(GPP_A6, NONE),
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
+	PAD_NC(GPP_A11, NONE),
+	PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
+	PAD_NC(GPP_A14, NONE),
+	PAD_NC(GPP_A15, NONE),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
+	PAD_NC(GPP_A17, NONE),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_NC(GPP_A19, NONE),
+	PAD_NC(GPP_A20, NONE),
+	PAD_NC(GPP_A21, NONE),
+	PAD_CFG_GPI(GPP_A22, NONE, DEEP), // SSD2_PCIE_WAKE#
+	PAD_NC(GPP_A23, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), // VRALERT#
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	//PAD_NC(GPP_B9, NONE),
+	//PAD_NC(GPP_B10, NONE),
+	PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // Top swap override
+	PAD_NC(GPP_B15, NONE),
+	PAD_NC(GPP_B16, NONE),
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST), // WLAN_RST#
+	PAD_NC(GPP_B18, NONE), // NO REBOOT strap
+	//PAD_NC(GPP_B19, NONE),
+	//PAD_NC(GPP_B20, NONE),
+	//PAD_NC(GPP_B21, NONE),
+	//PAD_NC(GPP_B22, NONE),
+	PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK_DDR
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // CMB_DATA_DDR
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST), // TLS CONFIDENTIALITY strap
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
+	PAD_NC(GPP_C5, NONE), // ESPI OR EC LESS strap
+	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
+	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
+	//PAD_NC(GPP_C8, NONE),
+	//PAD_NC(GPP_C9, NONE),
+	//PAD_NC(GPP_C10, NONE),
+	//PAD_NC(GPP_C11, NONE),
+	//PAD_NC(GPP_C12, NONE),
+	//PAD_NC(GPP_C13, NONE),
+	//PAD_NC(GPP_C14, NONE),
+	//PAD_NC(GPP_C15, NONE),
+	//PAD_NC(GPP_C16, NONE),
+	//PAD_NC(GPP_C17, NONE),
+	//PAD_NC(GPP_C18, NONE),
+	//PAD_NC(GPP_C19, NONE),
+	//PAD_NC(GPP_C20, NONE),
+	//PAD_NC(GPP_C21, NONE),
+	//PAD_NC(GPP_C22, NONE),
+	//PAD_NC(GPP_C23, NONE),
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
+	PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
+	PAD_NC(GPP_D3, NONE),
+	PAD_NC(GPP_D4, NONE),
+	//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
+	//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
+	//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_NC(GPP_D8, NONE),
+	PAD_NC(GPP_D9, NONE),
+	PAD_NC(GPP_D10, NONE),
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD2_PWR_EN
+	PAD_NC(GPP_D15, NONE),
+	PAD_CFG_GPO(GPP_D16, 1, DEEP), // SSD1_PWR_EN
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_CFG_GPO(GPP_D19, 0, DEEP), // SATA_LED#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST), // WIFI_RF_EN
+	PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
+	PAD_NC(GPP_E5, NONE),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP), // JTAG ODT DISABLE strap
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
+	PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
+	PAD_NC(GPP_E10, NONE),
+	PAD_CFG_GPI(GPP_E11, NONE,  DEEP), // BOARD_ID1
+	PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_NC(GPP_E13, NONE),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
+	PAD_NC(GPP_E15, NONE),
+	PAD_NC(GPP_E16, NONE),
+	PAD_NC(GPP_E17, NONE),
+	PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD
+	PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD
+	PAD_NC(GPP_E20, NONE),
+	PAD_NC(GPP_E21, NONE),
+	PAD_NC(GPP_E22, NONE),
+	PAD_NC(GPP_E23, NONE),
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
+	//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
+	//PAD_NC(GPP_F8, NONE),
+	PAD_NC(GPP_F9, NONE),
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST), // CARD_RTD3_RST#
+	PAD_NC(GPP_F11, NONE),
+	PAD_NC(GPP_F12, NONE),
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPO(GPP_F17, 1, PLTRST), // GPIO_SDCARD_EN
+	PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // CARD_CLKREQ#
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD2_RST#
+	PAD_NC(GPP_F21, NONE),
+	PAD_NC(GPP_F22, NONE),
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_CFG_GPO(GPP_H0, 1, PLTRST), // MS_SSD1_RST#
+	PAD_NC(GPP_H1, NONE),
+	PAD_CFG_GPO(GPP_H2, 1, PLTRST), // WLAN_RST#
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD
+	//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+	_PAD_CFG_STRUCT(GPP_H12, 0x44001500, 0x0000), // SATA1_DEVSLP1
+	PAD_NC(GPP_H13, NONE),
+	//PAD_NC(GPP_H14, NONE),
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	//PAD_NC(GPP_H16, NONE),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_NC(GPP_H19, NONE),
+	PAD_CFG_GPO(GPP_H20, 0, DEEP), // PM_CLKRUN#
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_NC(GPP_H23, NONE),
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE), // DMIC_CLK
+	PAD_NC(GPP_R7, NONE), // DMIC_DAT
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_NC(GPP_S6, NONE),
+	PAD_NC(GPP_S7, NONE),
+
+	/* ------- GPIO Group GPP_T ------- */
+	PAD_NC(GPP_T2, NONE),
+	PAD_NC(GPP_T3, NONE),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/adl-p/variants/lemp11/gpio_early.c b/src/mainboard/system76/adl-p/variants/lemp11/gpio_early.c
new file mode 100644
index 0000000000..c80c798b04
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/lemp11/gpio_early.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/adl-p/variants/lemp11/hda_verb.c b/src/mainboard/system76/adl-p/variants/lemp11/hda_verb.c
new file mode 100644
index 0000000000..d03c67acff
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/lemp11/hda_verb.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256,
+	0x15587718,
+	11,
+	AZALIA_SUBVENDOR(0, 0x15587718),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb b/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb
new file mode 100644
index 0000000000..5d0327b6b2
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb
@@ -0,0 +1,167 @@
+chip soc/intel/alderlake
+	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+		.tdp_pl1_override = 20,
+		.tdp_pl2_override = 46,
+		.tdp_pl4 = 65,
+	}"
+
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_A"
+	register "pmc_gpe0_dw1" = "PMC_GPP_R"
+	register "pmc_gpe0_dw2" = "PMC_GPD"
+
+	device domain 0 on
+		subsystemid 0x1558 0x7718 inherit
+
+		device ref pcie4_0 on
+			# PCIe PEG0 x4, Clock 0 (SSD2)
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST#
+				register "srcclk_pin" = "0" # SSD0_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref tcss_xhci on
+			register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+			chip drivers/usb/acpi
+				device ref tcss_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""TBT Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref tcss_usb3_port1 on end
+					end
+				end
+			end
+		end
+		device ref xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Left
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Right
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
+			register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Left
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Right
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
+			# ACPI
+			chip drivers/usb/acpi
+				device ref xhci_root_hub on
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Left""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-A Right""
+						register "type" = "UPC_TYPE_A"
+						device ref usb2_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb2_port3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 3G/LTE""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Camera""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB2 Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device ref usb2_port10 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Left""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-A Right""
+						register "type" = "UPC_TYPE_A"
+						device ref usb3_port2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Type-C""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device ref usb3_port3 on end
+					end
+				end
+			end
+		end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp5 on
+			# PCIe RP#5 x1, Clock 2 (WLAN)
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 2,
+				.clk_req = 2,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" # PCH_BT_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" # WLAN_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp6 on
+			# PCIe RP#6 x1, Clock 6 (CARD)
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 6,
+				.clk_req = 6,
+				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F17)" # GPIO_SDCARD_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # CARD_RTD3_RST#
+				register "srcclk_pin" = "6" # CARD_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pcie_rp9 on
+			# PCIe RP#9 x4, Clock 1 (SSD1)
+			register "pch_pcie_rp[PCH_RP(9)]" = "{
+				.clk_src = 1,
+				.clk_req = 1,
+				.flags = PCIE_RP_LTR,
+			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST#
+				register "srcclk_pin" = "1" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref pmc hidden
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						# J_TYPEC1
+						use usb2_port3 as usb2_port
+						use tcss_usb3_port1 as usb3_port
+						device generic 0 alias conn0 on end
+					end
+				end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/system76/adl-p/variants/lemp11/romstage.c b/src/mainboard/system76/adl-p/variants/lemp11/romstage.c
new file mode 100644
index 0000000000..dbc91a6ace
--- /dev/null
+++ b/src/mainboard/system76/adl-p/variants/lemp11/romstage.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR4,
+		.rcomp = { .resistor = 100, },
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_MIXED,
+		.cbfs_index = 0,
+		.smbus[1] = { .addr_dimm[0] = 0x52, },
+	};
+	const bool half_populated = false;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}