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* drop reset files from 945 mainboards (and use southbridge specific reset)

Browse Source 
* drop debug.c files from 945 mainboards (and share it in the northbridge code)
* adapt the mainboard and auto.c files for above changes.

Rather trivial 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-01-16 16:35:38 +00:00
committed by Stefan Reinauer
parent 42944c3989
commit 67cd802990
14 changed files with 41 additions and 323 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/d945gclf/Config.lb
View File

@@ -60,8 +60,6 @@ if CONFIG_GENERATE_ACPI_TABLES
object ./dsdt.o object ./dsdt.o
end end
object reset.o
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o makerule ./auto.o

1
src/mainboard/intel/d945gclf/Makefile.inc
View File

@@ -24,7 +24,6 @@
driver-y += mainboard.o driver-y += mainboard.o
driver-y += rtl8168.o driver-y += rtl8168.o
#obj-y += ../../../southbridge/intel/i82801gx/i82801gx_reset.c
obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o

8
src/mainboard/intel/d945gclf/auto.c
View File

@@ -20,6 +20,10 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct. // __PRE_RAM__ means: use "unsigned" for device, not a struct.
#define __PRE_RAM__ #define __PRE_RAM__
/* Configuration of the i945 driver */
#define CHIPSET_I945GC 1
#define CHANNEL_XOR_RANDOMIZATION 1
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <arch/io.h> #include <arch/io.h>
@@ -45,7 +49,6 @@
#include "lib/ramtest.c" #include "lib/ramtest.c"
#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
#include "reset.c"
#include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c" #include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
#include "northbridge/intel/i945/udelay.c" #include "northbridge/intel/i945/udelay.c"
@@ -77,12 +80,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#define CHANNEL_XOR_RANDOMIZATION 1
#include "northbridge/intel/i945/raminit.h" #include "northbridge/intel/i945/raminit.h"
#include "northbridge/intel/i945/raminit.c" #include "northbridge/intel/i945/raminit.c"
#include "northbridge/intel/i945/reset_test.c" #include "northbridge/intel/i945/reset_test.c"
#include "northbridge/intel/i945/errata.c" #include "northbridge/intel/i945/errata.c"
#include "debug.c" #include "northbridge/intel/i945/debug.c"
static void ich7_enable_lpc(void) static void ich7_enable_lpc(void)
{ {

126
src/mainboard/intel/d945gclf/debug.c
View File

@@ -1,126 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define SMBUS_MEM_DEVICE_START 0x50
#define SMBUS_MEM_DEVICE_END 0x53
#define SMBUS_MEM_DEVICE_INC 1
static void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
(dev >> 15) & 0x1f, (dev >> 12) & 7);
printk_debug(" [%04x:%04x]\r\n", id &0xffff, id >> 16);
}
}
static void dump_pci_device(unsigned dev)
{
int i;
printk_debug("PCI: %02x:%02x.%02x\r\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
for(i = 0; i <= 255; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
printk_debug("%02x:", i);
}
val = pci_read_config8(dev, i);
printk_debug(" %02x", val);
if ((i & 0x0f) == 0x0f) {
printk_debug("\r\n");
}
}
}
static void dump_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
}
}
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
printk_debug("\r\ndimm %02x", device);
for(i = 0; (i < 256) ; i++) {
if ((i % 16) == 0) {
printk_debug("\r\n%02x: ", i);
}
status = smbus_read_byte(device, i);
if (status < 0) {
printk_debug("bad device: %02x\r\n", -status);
break;
}
printk_debug("%02x ", status);
}
device += SMBUS_MEM_DEVICE_INC;
printk_debug("\r\n");
}
}
static void dump_mem(unsigned start, unsigned end)
{
unsigned i;
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%08x:", i);
#else
print_debug("\r\n");
print_debug_hex32(i);
print_debug(":");
#endif
}
#if CONFIG_USE_INIT
printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
print_debug_hex8((unsigned char)*((unsigned char *)i));
#endif
}
print_debug("\r\n");
}

28
src/mainboard/intel/d945gclf/power_reset_check.c
View File

@@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
static void power_down_reset_check(void)
{
uint8_t cmos;
cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
printk_debug("Boot byte = %x\r\n", cmos);
if((cmos>2)&&(cmos&1)) full_reset();
}

31
src/mainboard/intel/d945gclf/reset.c
View File

@@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
void soft_reset(void)
{
outb(0x04, 0xcf9);
}
void hard_reset(void)
{
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}

31
src/mainboard/intel/eagleheights/power_reset_check.c
View File

@@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
static void power_down_reset_check(void)
{
uint8_t cmos;
cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
printk_debug("Boot byte = %x\r\n", cmos);
if((cmos>2)&&(cmos&1)) full_reset();
}

2
src/mainboard/kontron/986lcd-m/Config.lb
View File

@@ -62,8 +62,6 @@ if CONFIG_GENERATE_ACPI_TABLES
object ./dsdt.o object ./dsdt.o
end end
if CONFIG_HAVE_HARD_RESET object reset.o end
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o makerule ./auto.o

2
src/mainboard/kontron/986lcd-m/Makefile.inc
View File

@@ -26,13 +26,11 @@
driver-y += mainboard.o driver-y += mainboard.o
driver-y += rtl8168.o driver-y += rtl8168.o
#obj-y += ../../../southbridge/intel/i82801gx/i82801gx_reset.c
obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.o
obj-$(CONFIG_HAVE_HARD_RESET) += reset.o
smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o

27
src/mainboard/kontron/986lcd-m/auto.c
View File

@@ -22,6 +22,19 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct. // __PRE_RAM__ means: use "unsigned" for device, not a struct.
#define __PRE_RAM__ #define __PRE_RAM__
/* Configuration of the i945 driver */
#define CHIPSET_I945GM 1
/* Usually system firmware turns off system memory clock signals to
* unused SO-DIMM slots to reduce EMI and power consumption.
* However, the Kontron 986LCD-M does not like unused clock signals to
* be disabled. If other similar mainboard occur, it would make sense
* to make this an entry in the sysinfo structure, and pre-initialize that
* structure in the mainboard's auto.c main() function. For now a
* #define will do.
*/
#define OVERRIDE_CLOCK_DISABLE 1
#define CHANNEL_XOR_RANDOMIZATION 1
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <arch/io.h> #include <arch/io.h>
@@ -47,7 +60,6 @@
#include "lib/ramtest.c" #include "lib/ramtest.c"
#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
#include "reset.c"
#include "superio/winbond/w83627thg/w83627thg_early_serial.c" #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
#include "northbridge/intel/i945/udelay.c" #include "northbridge/intel/i945/udelay.c"
@@ -78,22 +90,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
/* Usually system firmware turns off system memory clock signals to
* unused SO-DIMM slots to reduce EMI and power consumption.
* However, the Kontron 986LCD-M does not like unused clock signals to
* be disabled. If other similar mainboard occur, it would make sense
* to make this an entry in the sysinfo structure, and pre-initialize that
* structure in the mainboard's auto.c main() function. For now a
* #define will do.
*/
#define OVERRIDE_CLOCK_DISABLE 1
#define CHANNEL_XOR_RANDOMIZATION 1
#include "northbridge/intel/i945/raminit.h" #include "northbridge/intel/i945/raminit.h"
#include "northbridge/intel/i945/raminit.c" #include "northbridge/intel/i945/raminit.c"
#include "northbridge/intel/i945/reset_test.c" #include "northbridge/intel/i945/reset_test.c"
#include "northbridge/intel/i945/errata.c" #include "northbridge/intel/i945/errata.c"
#include "debug.c" #include "northbridge/intel/i945/debug.c"
static void ich7_enable_lpc(void) static void ich7_enable_lpc(void)
{ {

31
src/mainboard/kontron/986lcd-m/power_reset_check.c
View File

@@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
static void power_down_reset_check(void)
{
uint8_t cmos;
cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
printk_debug("Boot byte = %x\r\n", cmos);
if((cmos>2)&&(cmos&1)) full_reset();
}

33
src/mainboard/kontron/986lcd-m/reset.c
View File

@@ -1,33 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <arch/io.h>
void soft_reset(void)
{
outb(0x04, 0xcf9);
}
void hard_reset(void)
{
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}

29
src/mainboard/kontron/986lcd-m/debug.c → src/northbridge/intel/i945/debug.c
View File

@@ -38,7 +38,7 @@ static void print_pci_devices(void)
} }
printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff, printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
(dev >> 15) & 0x1f, (dev >> 12) & 7); (dev >> 15) & 0x1f, (dev >> 12) & 7);
printk_debug(" [%04x:%04x]\r\n", id &0xffff, id >> 16); printk_debug(" [%04x:%04x]\n", id &0xffff, id >> 16);
} }
} }
@@ -46,7 +46,7 @@ static void dump_pci_device(unsigned dev)
{ {
int i; int i;
printk_debug("PCI: %02x:%02x.%02x\r\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7); printk_debug("PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
for(i = 0; i <= 255; i++) { for(i = 0; i <= 255; i++) {
unsigned char val; unsigned char val;
@@ -56,7 +56,7 @@ static void dump_pci_device(unsigned dev)
val = pci_read_config8(dev, i); val = pci_read_config8(dev, i);
printk_debug(" %02x", val); printk_debug(" %02x", val);
if ((i & 0x0f) == 0x0f) { if ((i & 0x0f) == 0x0f) {
printk_debug("\r\n"); printk_debug("\n");
} }
} }
} }
@@ -85,21 +85,21 @@ void dump_spd_registers(void)
while(device <= SMBUS_MEM_DEVICE_END) { while(device <= SMBUS_MEM_DEVICE_END) {
int status = 0; int status = 0;
int i; int i;
printk_debug("\r\ndimm %02x", device); printk_debug("\ndimm %02x", device);
for(i = 0; (i < 256) ; i++) { for(i = 0; (i < 256) ; i++) {
if ((i % 16) == 0) { if ((i % 16) == 0) {
printk_debug("\r\n%02x: ", i); printk_debug("\n%02x: ", i);
} }
status = smbus_read_byte(device, i); status = smbus_read_byte(device, i);
if (status < 0) { if (status < 0) {
printk_debug("bad device: %02x\r\n", -status); printk_debug("bad device: %02x\n", -status);
break; break;
} }
printk_debug("%02x ", status); printk_debug("%02x ", status);
} }
device += SMBUS_MEM_DEVICE_INC; device += SMBUS_MEM_DEVICE_INC;
printk_debug("\r\n"); printk_debug("\n");
} }
} }
@@ -109,20 +109,9 @@ static void dump_mem(unsigned start, unsigned end)
print_debug("dump_mem:"); print_debug("dump_mem:");
for(i=start;i<end;i++) { for(i=start;i<end;i++) {
if((i & 0xf)==0) { if((i & 0xf)==0) {
#if CONFIG_USE_INIT printk_debug("\n%08x:", i);
printk_debug("\r\n%08x:", i);
#else
print_debug("\r\n");
print_debug_hex32(i);
print_debug(":");
#endif
} }
#if CONFIG_USE_INIT
printk_debug(" %02x", (unsigned char)*((unsigned char *)i)); printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
print_debug_hex8((unsigned char)*((unsigned char *)i));
#endif
} }
print_debug("\r\n"); print_debug("\n");
} }

13
src/southbridge/intel/i82801gx/i82801gx_reset.c
View File

@@ -20,8 +20,21 @@
#include <arch/io.h> #include <arch/io.h>
void soft_reset(void)
{
outb(0x04, 0xcf9);
}
#if 0
void hard_reset(void) void hard_reset(void)
{ {
/* Try rebooting through port 0xcf9. */ /* Try rebooting through port 0xcf9. */
outb((1 << 2) | (1 << 1), 0xcf9); outb((1 << 2) | (1 << 1), 0xcf9);
} }
#endif
void hard_reset(void)
{
outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}