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Remove leftover Intel CPU support

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Change-Id: I6ac67137d5f5c63dbc4fc54eacb3e326ccf423d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
2018-05-24 18:20:46 +03:00
parent 6308e0e92f
commit 688d004c4f
10 changed files with 0 additions and 205 deletions
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7
src/cpu/intel/Kconfig
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@ -22,21 +22,14 @@ source src/cpu/intel/model_f4x/Kconfig
source src/cpu/intel/ep80579/Kconfig source src/cpu/intel/ep80579/Kconfig
source src/cpu/intel/haswell/Kconfig source src/cpu/intel/haswell/Kconfig
# Sockets/Slots # Sockets/Slots
source src/cpu/intel/slot_2/Kconfig
source src/cpu/intel/slot_1/Kconfig source src/cpu/intel/slot_1/Kconfig
source src/cpu/intel/socket_BGA956/Kconfig source src/cpu/intel/socket_BGA956/Kconfig
source src/cpu/intel/socket_BGA1284/Kconfig source src/cpu/intel/socket_BGA1284/Kconfig
source src/cpu/intel/socket_FC_PGA370/Kconfig
source src/cpu/intel/socket_FCBGA559/Kconfig source src/cpu/intel/socket_FCBGA559/Kconfig
source src/cpu/intel/socket_FCBGA1023/Kconfig source src/cpu/intel/socket_FCBGA1023/Kconfig
source src/cpu/intel/socket_mFCBGA479/Kconfig
source src/cpu/intel/socket_mFCPGA478/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig
source src/cpu/intel/socket_mPGA478/Kconfig
source src/cpu/intel/socket_mPGA478MN/Kconfig source src/cpu/intel/socket_mPGA478MN/Kconfig
source src/cpu/intel/socket_mPGA479M/Kconfig
source src/cpu/intel/socket_mPGA603/Kconfig
source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_mPGA604/Kconfig
source src/cpu/intel/socket_PGA370/Kconfig
source src/cpu/intel/socket_441/Kconfig source src/cpu/intel/socket_441/Kconfig
source src/cpu/intel/socket_LGA1155/Kconfig source src/cpu/intel/socket_LGA1155/Kconfig
source src/cpu/intel/socket_LGA775/Kconfig source src/cpu/intel/socket_LGA775/Kconfig

8
src/cpu/intel/Makefile.inc
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@ -7,15 +7,11 @@ subdirs-$(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) += fit
subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA1023) += socket_FCBGA1023 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA1023) += socket_FCBGA1023
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B
subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989 subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
@ -25,10 +21,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
#socket_mPGA604_533Mhz
#socket_mPGA604_800Mhz

22
src/cpu/intel/slot_2/Kconfig
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@ -1,22 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config CPU_INTEL_SLOT_2
bool
config DCACHE_RAM_SIZE
hex
default 0x01000
depends on CPU_INTEL_SLOT_2

24
src/cpu/intel/slot_2/Makefile.inc
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@ -1,24 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ramstage-y += slot_2.c
subdirs-y += ../model_6xx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode

19
src/cpu/intel/slot_2/slot_2.c
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@ -1,19 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
struct chip_operations cpu_intel_slot_2_ops = {
CHIP_NAME("Slot 2 CPU")
};

33
src/cpu/intel/socket_FC_PGA370/Kconfig
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@ -1,33 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config CPU_INTEL_SOCKET_FC_PGA370
bool
select CPU_INTEL_MODEL_68X
select MMX
select SSE
if CPU_INTEL_SOCKET_FC_PGA370
config DCACHE_RAM_BASE
hex
default 0xc8000
config DCACHE_RAM_SIZE
hex
default 0x08000
endif

26
src/cpu/intel/socket_FC_PGA370/Makefile.inc
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@ -1,26 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
subdirs-y += ../model_68x
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
romstage-y += ../car/romstage_legacy.c

36
src/cpu/intel/socket_PGA370/Kconfig
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@ -1,36 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config CPU_INTEL_SOCKET_PGA370
bool
select CPU_INTEL_MODEL_6XX
select MMX
if CPU_INTEL_SOCKET_PGA370
# Not all CPUs for Socket 370 can do SSE2
config SSE2
bool
default n
config DCACHE_RAM_BASE
hex
default 0xcf000
config DCACHE_RAM_SIZE
hex
default 0x01000
endif

26
src/cpu/intel/socket_PGA370/Makefile.inc
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@ -1,26 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
subdirs-y += ../model_6xx
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
subdirs-y += ../microcode
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
romstage-y += ../car/romstage_legacy.c

4
src/cpu/intel/socket_mPGA478/Kconfig
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@ -1,4 +0,0 @@
config CPU_INTEL_SOCKET_MPGA478
bool
select CPU_INTEL_MODEL_69X
select CPU_INTEL_MODEL_6DX