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make log message a little prettier

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
2004-03-25 18:04:18 +00:00
parent edeff59c72
commit 68a5e08499
10 changed files with 300 additions and 302 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/amd/quartet/auto.c
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@@ -217,7 +217,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0

2
src/mainboard/amd/solo/auto.c
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@@ -116,7 +116,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0

35
src/mainboard/arima/hdama/auto.c
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@@ -39,6 +39,10 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
} }
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static void memreset_setup(void) static void memreset_setup(void)
{ {
if (is_cpu_pre_c0()) { if (is_cpu_pre_c0()) {
@@ -46,8 +50,7 @@ static void memreset_setup(void)
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */ /* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} } else {
else {
/* Ensure the CPU has controll of the memory lines */ /* Ensure the CPU has controll of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
} }
@@ -87,21 +90,21 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
* [3] Route to Link 2 * [3] Route to Link 2
*/ */
uint32_t ret=0x00010101; /* default row entry */ uint32_t ret = 0x00010101; /* default row entry */
static const unsigned int rows_2p[2][2] = { static const unsigned int rows_2p[2][2] = {
{ 0x00050101, 0x00010404 }, { 0x00050101, 0x00010404 },
{ 0x00010404, 0x00050101 } { 0x00010404, 0x00050101 }
}; };
if(maxnodes > 2) { if (maxnodes > 2) {
print_debug("this mainboard is only designed for 2 cpus\r\n"); print_debug("this mainboard is only designed for 2 cpus\r\n");
maxnodes=2; maxnodes = 2;
} }
if (!(node >= maxnodes || row >= maxnodes)) { if (!(node >= maxnodes || row >= maxnodes)) {
ret=rows_2p[node][row]; ret = rows_2p[node][row];
} }
return ret; return ret;
@@ -121,18 +124,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
#define FIRST_CPU 1 #define FIRST_CPU 1
#define SECOND_CPU 1 #define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
static void main(void) static void main(void)
{ {
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
*/
static const struct mem_controller cpu[] = { static const struct mem_controller cpu[] = {
#if FIRST_CPU #if FIRST_CPU
{ {
@@ -157,40 +153,47 @@ static void main(void)
}, },
#endif #endif
}; };
int needs_reset; int needs_reset;
enable_lapic(); enable_lapic();
init_timer(); init_timer();
if (cpu_init_detected()) { if (cpu_init_detected()) {
asm("jmp __cpu_reset"); asm("jmp __cpu_reset");
} }
distinguish_cpu_resets(); distinguish_cpu_resets();
if (!boot_cpu()) { if (!boot_cpu()) {
stop_this_cpu(); stop_this_cpu();
} }
pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE); pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
setup_default_resource_map(); setup_default_resource_map();
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0
print_pci_devices(); print_pci_devices();
#endif #endif
enable_smbus(); enable_smbus();
#if 0 #if 0
dump_spd_registers(&cpu[0]); dump_spd_registers(&cpu[0]);
#endif #endif
memreset_setup(); memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0 #if 0
dump_pci_devices(); dump_pci_devices();
#endif
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 2)); dump_pci_device(PCI_DEV(0, 0x18, 2));
#endif #endif

2
src/mainboard/newisys/khepri/auto.c
View File

@@ -171,7 +171,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0

2
src/mainboard/tyan/s2880/auto.c
View File

@@ -166,7 +166,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\t");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2881/auto.c
View File

@@ -165,7 +165,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\t");
soft_reset(); soft_reset();
} }

2
src/mainboard/tyan/s2882/auto.c
View File

@@ -172,7 +172,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0

58
src/mainboard/tyan/s2885/auto.c
View File

@@ -1,5 +1,4 @@
#define ASSEMBLY 1 #define ASSEMBLY 1
#include <stdint.h> #include <stdint.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
@@ -40,24 +39,23 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1); pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
} }
#define REV_B_RESET 0
static void memreset_setup(void) static void memreset_setup(void)
{ {
#if REV_B_RESET==1 if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
#else outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 } else {
#endif outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
} }
static void memreset(int controllers, const struct mem_controller *ctrl) static void memreset(int controllers, const struct mem_controller *ctrl)
{ {
udelay(800); if (is_cpu_pre_c0()) {
#if REV_B_RESET==1 udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
#endif udelay(90);
udelay(90); }
} }
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
@@ -84,21 +82,20 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
* [3] Route to Link 2 * [3] Route to Link 2
*/ */
uint32_t ret=0x00010101; /* default row entry */ uint32_t ret = 0x00010101; /* default row entry */
static const unsigned int rows_2p[2][2] = { static const unsigned int rows_2p[2][2] = {
{ 0x00050101, 0x00010404 }, { 0x00050101, 0x00010404 },
{ 0x00010404, 0x00050101 } { 0x00010404, 0x00050101 }
}; };
if(maxnodes>2) { if (maxnodes > 2) {
print_debug("this mainboard is only designed for 2 cpus\r\n"); print_debug("this mainboard is only designed for 2 cpus\r\n");
maxnodes=2; maxnodes = 2;
} }
if (!(node >= maxnodes || row >= maxnodes)) {
if (!(node>=maxnodes || row>=maxnodes)) { ret = rows_2p[node][row];
ret=rows_2p[node][row];
} }
return ret; return ret;
@@ -166,24 +163,29 @@ static void main(void)
}, },
}; };
int needs_reset; int needs_reset;
enable_lapic(); enable_lapic();
init_timer(); init_timer();
if (cpu_init_detected()) { if (cpu_init_detected()) {
asm("jmp __cpu_reset"); asm("jmp __cpu_reset");
} }
distinguish_cpu_resets(); distinguish_cpu_resets();
if (!boot_cpu()) { if (!boot_cpu()) {
stop_this_cpu(); stop_this_cpu();
} }
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
setup_s2885_resource_map(); setup_s2885_resource_map();
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
// needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0); // needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0])); needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
#if 0 #if 0
@@ -194,18 +196,19 @@ static void main(void)
#if 0 #if 0
print_pci_devices(); print_pci_devices();
#endif #endif
enable_smbus(); enable_smbus();
#if 0 #if 0
dump_spd_registers(&cpu[0]); dump_spd_registers(&cpu[0]);
#endif #endif
memreset_setup(); memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0 #if 1
dump_pci_devices(); dump_pci_devices();
#endif //dump_pci_device(PCI_DEV(0, 0x18, 1));
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 1));
#endif #endif
/* Check all of memory */ /* Check all of memory */
@@ -216,11 +219,7 @@ static void main(void)
print_debug_hex32(msr.hi); print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo); print_debug_hex32(msr.lo);
print_debug("\r\n"); print_debug("\r\n");
#endif
/*
#if 0
ram_check(0x00000000, msr.lo+(msr.hi<<32)); ram_check(0x00000000, msr.lo+(msr.hi<<32));
#else
#if TOTAL_CPUS < 2 #if TOTAL_CPUS < 2
// Check 16MB of memory @ 0 // Check 16MB of memory @ 0
ram_check(0x00000000, 0x00100000); ram_check(0x00000000, 0x00100000);
@@ -229,5 +228,4 @@ static void main(void)
ram_check(0x80000000, 0x80100000); ram_check(0x80000000, 0x80100000);
#endif #endif
#endif #endif
*/
} }

495
src/mainboard/tyan/s2885/resourcemap.c
View File

@@ -6,261 +6,258 @@
static void setup_s2885_resource_map(void) static void setup_s2885_resource_map(void)
{ {
static const unsigned int register_values[] = { static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which contain the enables */ /* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers /* DRAM Limit i Registers
* F1:0x44 i = 0 * F1:0x44 i = 0
* F1:0x4C i = 1 * F1:0x4C i = 1
* F1:0x54 i = 2 * F1:0x54 i = 2
* F1:0x5C i = 3 * F1:0x5C i = 3
* F1:0x64 i = 4 * F1:0x64 i = 4
* F1:0x6C i = 5 * F1:0x6C i = 5
* F1:0x74 i = 6 * F1:0x74 i = 6
* F1:0x7C i = 7 * F1:0x7C i = 7
* [ 2: 0] Destination Node ID * [ 2: 0] Destination Node ID
* 000 = Node 0 * 000 = Node 0
* 001 = Node 1 * 001 = Node 1
* 010 = Node 2 * 010 = Node 2
* 011 = Node 3 * 011 = Node 3
* 100 = Node 4 * 100 = Node 4
* 101 = Node 5 * 101 = Node 5
* 110 = Node 6 * 110 = Node 6
* 111 = Node 7 * 111 = Node 7
* [ 7: 3] Reserved * [ 7: 3] Reserved
* [10: 8] Interleave select * [10: 8] Interleave select
* specifies the values of A[14:12] to use with interleave enable. * specifies the values of A[14:12] to use with interleave enable.
* [15:11] Reserved * [15:11] Reserved
* [31:16] DRAM Limit Address i Bits 39-24 * [31:16] DRAM Limit Address i Bits 39-24
* This field defines the upper address bits of a 40 bit address * This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region. * that define the end of the DRAM region.
*/ */
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
/* DRAM Base i Registers /* DRAM Base i Registers
* F1:0x40 i = 0 * F1:0x40 i = 0
* F1:0x48 i = 1 * F1:0x48 i = 1
* F1:0x50 i = 2 * F1:0x50 i = 2
* F1:0x58 i = 3 * F1:0x58 i = 3
* F1:0x60 i = 4 * F1:0x60 i = 4
* F1:0x68 i = 5 * F1:0x68 i = 5
* F1:0x70 i = 6 * F1:0x70 i = 6
* F1:0x78 i = 7 * F1:0x78 i = 7
* [ 0: 0] Read Enable * [ 0: 0] Read Enable
* 0 = Reads Disabled * 0 = Reads Disabled
* 1 = Reads Enabled * 1 = Reads Enabled
* [ 1: 1] Write Enable * [ 1: 1] Write Enable
* 0 = Writes Disabled * 0 = Writes Disabled
* 1 = Writes Enabled * 1 = Writes Enabled
* [ 7: 2] Reserved * [ 7: 2] Reserved
* [10: 8] Interleave Enable * [10: 8] Interleave Enable
* 000 = No interleave * 000 = No interleave
* 001 = Interleave on A[12] (2 nodes) * 001 = Interleave on A[12] (2 nodes)
* 010 = reserved * 010 = reserved
* 011 = Interleave on A[12] and A[14] (4 nodes) * 011 = Interleave on A[12] and A[14] (4 nodes)
* 100 = reserved * 100 = reserved
* 101 = reserved * 101 = reserved
* 110 = reserved * 110 = reserved
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
* [15:11] Reserved * [15:11] Reserved
* [13:16] DRAM Base Address i Bits 39-24 * [13:16] DRAM Base Address i Bits 39-24
* This field defines the upper address bits of a 40-bit address * This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region. * that define the start of the DRAM region.
*/ */
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
/* Memory-Mapped I/O Limit i Registers /* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0 * F1:0x84 i = 0
* F1:0x8C i = 1 * F1:0x8C i = 1
* F1:0x94 i = 2 * F1:0x94 i = 2
* F1:0x9C i = 3 * F1:0x9C i = 3
* F1:0xA4 i = 4 * F1:0xA4 i = 4
* F1:0xAC i = 5 * F1:0xAC i = 5
* F1:0xB4 i = 6 * F1:0xB4 i = 6
* F1:0xBC i = 7 * F1:0xBC i = 7
* [ 2: 0] Destination Node ID * [ 2: 0] Destination Node ID
* 000 = Node 0 * 000 = Node 0
* 001 = Node 1 * 001 = Node 1
* 010 = Node 2 * 010 = Node 2
* 011 = Node 3 * 011 = Node 3
* 100 = Node 4 * 100 = Node 4
* 101 = Node 5 * 101 = Node 5
* 110 = Node 6 * 110 = Node 6
* 111 = Node 7 * 111 = Node 7
* [ 3: 3] Reserved * [ 3: 3] Reserved
* [ 5: 4] Destination Link ID * [ 5: 4] Destination Link ID
* 00 = Link 0 * 00 = Link 0
* 01 = Link 1 * 01 = Link 1
* 10 = Link 2 * 10 = Link 2
* 11 = Reserved * 11 = Reserved
* [ 6: 6] Reserved * [ 6: 6] Reserved
* [ 7: 7] Non-Posted * [ 7: 7] Non-Posted
* 0 = CPU writes may be posted * 0 = CPU writes may be posted
* 1 = CPU writes must be non-posted * 1 = CPU writes must be non-posted
* [31: 8] Memory-Mapped I/O Limit Address i (39-16) * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit address that * This field defines the upp adddress bits of a 40-bit address that
* defines the end of a memory-mapped I/O region n * defines the end of a memory-mapped I/O region n
*/ */
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20, PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
/* Memory-Mapped I/O Base i Registers /* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0 * F1:0x80 i = 0
* F1:0x88 i = 1 * F1:0x88 i = 1
* F1:0x90 i = 2 * F1:0x90 i = 2
* F1:0x98 i = 3 * F1:0x98 i = 3
* F1:0xA0 i = 4 * F1:0xA0 i = 4
* F1:0xA8 i = 5 * F1:0xA8 i = 5
* F1:0xB0 i = 6 * F1:0xB0 i = 6
* F1:0xB8 i = 7 * F1:0xB8 i = 7
* [ 0: 0] Read Enable * [ 0: 0] Read Enable
* 0 = Reads disabled * 0 = Reads disabled
* 1 = Reads Enabled * 1 = Reads Enabled
* [ 1: 1] Write Enable * [ 1: 1] Write Enable
* 0 = Writes disabled * 0 = Writes disabled
* 1 = Writes Enabled * 1 = Writes Enabled
* [ 2: 2] Cpu Disable * [ 2: 2] Cpu Disable
* 0 = Cpu can use this I/O range * 0 = Cpu can use this I/O range
* 1 = Cpu requests do not use this I/O range * 1 = Cpu requests do not use this I/O range
* [ 3: 3] Lock * [ 3: 3] Lock
* 0 = base/limit registers i are read/write * 0 = base/limit registers i are read/write
* 1 = base/limit registers i are read-only * 1 = base/limit registers i are read-only
* [ 7: 4] Reserved * [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16) * [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit address * This field defines the upper address bits of a 40bit address
* that defines the start of memory-mapped I/O region i * that defines the start of memory-mapped I/O region i
*/ */
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers /* PCI I/O Limit i Registers
* F1:0xC4 i = 0 * F1:0xC4 i = 0
* F1:0xCC i = 1 * F1:0xCC i = 1
* F1:0xD4 i = 2 * F1:0xD4 i = 2
* F1:0xDC i = 3 * F1:0xDC i = 3
* [ 2: 0] Destination Node ID * [ 2: 0] Destination Node ID
* 000 = Node 0 * 000 = Node 0
* 001 = Node 1 * 001 = Node 1
* 010 = Node 2 * 010 = Node 2
* 011 = Node 3 * 011 = Node 3
* 100 = Node 4 * 100 = Node 4
* 101 = Node 5 * 101 = Node 5
* 110 = Node 6 * 110 = Node 6
* 111 = Node 7 * 111 = Node 7
* [ 3: 3] Reserved * [ 3: 3] Reserved
* [ 5: 4] Destination Link ID * [ 5: 4] Destination Link ID
* 00 = Link 0 * 00 = Link 0
* 01 = Link 1 * 01 = Link 1
* 10 = Link 2 * 10 = Link 2
* 11 = reserved * 11 = reserved
* [11: 6] Reserved * [11: 6] Reserved
* [24:12] PCI I/O Limit Address i * [24:12] PCI I/O Limit Address i
* This field defines the end of PCI I/O region n * This field defines the end of PCI I/O region n
* [31:25] Reserved * [31:25] Reserved
*/ */
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020, PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
/* PCI I/O Base i Registers /* PCI I/O Base i Registers
* F1:0xC0 i = 0 * F1:0xC0 i = 0
* F1:0xC8 i = 1 * F1:0xC8 i = 1
* F1:0xD0 i = 2 * F1:0xD0 i = 2
* F1:0xD8 i = 3 * F1:0xD8 i = 3
* [ 0: 0] Read Enable * [ 0: 0] Read Enable
* 0 = Reads Disabled * 0 = Reads Disabled
* 1 = Reads Enabled * 1 = Reads Enabled
* [ 1: 1] Write Enable * [ 1: 1] Write Enable
* 0 = Writes Disabled * 0 = Writes Disabled
* 1 = Writes Enabled * 1 = Writes Enabled
* [ 3: 2] Reserved * [ 3: 2] Reserved
* [ 4: 4] VGA Enable * [ 4: 4] VGA Enable
* 0 = VGA matches Disabled * 0 = VGA matches Disabled
* 1 = matches all address < 64K and where A[9:0] is in the * 1 = matches all address < 64K and where A[9:0] is in the
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
* [ 5: 5] ISA Enable * [ 5: 5] ISA Enable
* 0 = ISA matches Disabled * 0 = ISA matches Disabled
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
* from matching agains this base/limit pair * from matching agains this base/limit pair
* [11: 6] Reserved * [11: 6] Reserved
* [24:12] PCI I/O Base i * [24:12] PCI I/O Base i
* This field defines the start of PCI I/O region n * This field defines the start of PCI I/O region n
* [31:25] Reserved * [31:25] Reserved
*/ */
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
/* Config Base and Limit i Registers /* Config Base and Limit i Registers
* F1:0xE0 i = 0 * F1:0xE0 i = 0
* F1:0xE4 i = 1 * F1:0xE4 i = 1
* F1:0xE8 i = 2 * F1:0xE8 i = 2
* F1:0xEC i = 3 * F1:0xEC i = 3
* [ 0: 0] Read Enable * [ 0: 0] Read Enable
* 0 = Reads Disabled * 0 = Reads Disabled
* 1 = Reads Enabled * 1 = Reads Enabled
* [ 1: 1] Write Enable * [ 1: 1] Write Enable
* 0 = Writes Disabled * 0 = Writes Disabled
* 1 = Writes Enabled * 1 = Writes Enabled
* [ 2: 2] Device Number Compare Enable * [ 2: 2] Device Number Compare Enable
* 0 = The ranges are based on bus number * 0 = The ranges are based on bus number
* 1 = The ranges are ranges of devices on bus 0 * 1 = The ranges are ranges of devices on bus 0
* [ 3: 3] Reserved * [ 3: 3] Reserved
* [ 6: 4] Destination Node * [ 6: 4] Destination Node
* 000 = Node 0 * 000 = Node 0
* 001 = Node 1 * 001 = Node 1
* 010 = Node 2 * 010 = Node 2
* 011 = Node 3 * 011 = Node 3
* 100 = Node 4 * 100 = Node 4
* 101 = Node 5 * 101 = Node 5
* 110 = Node 6 * 110 = Node 6
* 111 = Node 7 * 111 = Node 7
* [ 7: 7] Reserved * [ 7: 7] Reserved
* [ 9: 8] Destination Link * [ 9: 8] Destination Link
* 00 = Link 0 * 00 = Link 0
* 01 = Link 1 * 01 = Link 1
* 10 = Link 2 * 10 = Link 2
* 11 - Reserved * 11 - Reserved
* [15:10] Reserved * [15:10] Reserved
* [23:16] Bus Number Base i * [23:16] Bus Number Base i
* This field defines the lowest bus number in configuration region i * This field defines the lowest bus number in configuration region i
* [31:24] Bus Number Limit i * [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i * This field defines the highest bus number in configuration regin i
*/ */
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04010207, PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04010207,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050007, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050007,
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04000203, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050003, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x00000203,
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
}; };
int max; int max;
max = sizeof(register_values)/sizeof(register_values[0]); max = sizeof(register_values)/sizeof(register_values[0]);
setup_resource_map(register_values, max); setup_resource_map(register_values, max);

2
src/mainboard/tyan/s4880/auto.c
View File

@@ -216,7 +216,7 @@ static void main(void)
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
if (needs_reset) { if (needs_reset) {
print_info("ht reset -"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }