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soc/amd/picasso: add UPD for RV2 USB3 phy setting adjust

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add UPD for RV2 USB3 phy setting adjust.

Note: it only for RV2 silicon and not available for RV/PCO.

Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
	-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
	-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1

BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz

Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris Wang
2021-02-03 04:32:06 +08:00
committed by Martin Roth
parent 4cecca4925
commit 68d68f1d7c
5 changed files with 143 additions and 1 deletions
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13
src/vendorcode/amd/fsp/picasso/FspsUpd.h
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@ -12,6 +12,7 @@
#define FSPS_UPD_DXIO_DESCRIPTOR_COUNT 8
#define FSPS_UPD_DDI_DESCRIPTOR_COUNT 4
#define FSPS_UPD_USB2_PORT_COUNT 6
#define FSPS_UPD_RV2_USB3_PORT_COUNT 4
typedef struct __packed {
/** Offset 0x0020**/ uint32_t emmc0_mode;
@ -54,7 +55,17 @@ typedef struct __packed {
/** Offset 0x0139**/ uint8_t pwron_varybl_to_blon;
/** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff;
/** Offset 0x013B**/ uint8_t min_allowed_bl_level;
/** Offset 0x013C**/ uint8_t UnusedUpdSpace0[20];
/** Offset 0x013C**/ uint8_t usb_3_phy_enable;
/** Offset 0x013D**/ uint8_t usb_3_port_phy_tune[FSPS_UPD_RV2_USB3_PORT_COUNT][2];
/** Offset 0x0145**/ uint8_t usb_3_rx_vref_ctrl;
/** Offset 0x0146**/ uint8_t usb_3_rx_vref_ctrl_en;
/** Offset 0x0147**/ uint8_t usb_3_tx_vboost_lvl;
/** Offset 0x0148**/ uint8_t usb_3_tx_vboost_lvl_en;
/** Offset 0x0149**/ uint8_t usb_3_rx_vref_ctrl_x;
/** Offset 0x014A**/ uint8_t usb_3_rx_vref_ctrl_en_x;
/** Offset 0x014B**/ uint8_t usb_3_tx_vboost_lvl_x;
/** Offset 0x014C**/ uint8_t usb_3_tx_vboost_lvl_en_x;
/** Offset 0x014D**/ uint8_t UnusedUpdSpace0[3];
/** Offset 0x0150**/ uint16_t UpdTerminator;
} FSP_S_CONFIG;