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Revert "model_206ax: Use parallel MP init"

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This reverts commit 5fbe788bae.
This commit was submitted without its parent being submitted,
resulting in coreboot not building.

Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
2018-04-11 13:03:34 +02:00
parent 5fbe788bae
commit 68f688896c
12 changed files with 93 additions and 194 deletions
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11
src/cpu/intel/smm/gen1/smi.h
View File

@@ -11,10 +11,6 @@
* GNU General Public License for more details.
*/
#include <device/device.h>
void bsp_init_and_start_aps(struct bus *cpu_bus);
/* These helpers are for performing SMM relocation. */
void southbridge_smm_init(void);
void southbridge_trigger_smi(void);
@@ -22,10 +18,3 @@ void southbridge_clear_smi_status(void);
u32 northbridge_get_tseg_base(void);
int cpu_get_apic_id_map(int *apic_id_map);
void northbridge_write_smram(u8 smram);
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size);
void smm_initialize(void);
void southbridge_smm_clear_state(void);
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase);
void smm_relocate(void);

77
src/cpu/intel/smm/gen1/smmrelocate.c
View File

@@ -23,12 +23,10 @@
#include <device/pci.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <console/console.h>
#include <smp/node.h>
#include "smi.h"
#define SMRR_SUPPORTED (1 << 11)
@@ -294,78 +292,3 @@ void smm_lock(void)
northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG);
}
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
fill_in_relocation_params(&smm_reloc_params);
setup_ied_area(&smm_reloc_params);
*perm_smbase = smm_reloc_params.smram_base;
*perm_smsize = smm_reloc_params.smram_size;
*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
}
void smm_initialize(void)
{
/* Clear the SMM state in the southbridge. */
southbridge_smm_clear_state();
/*
* Run the relocation handler for on the BSP to check and set up
* parallel SMM relocation.
*/
smm_initiate_relocation();
}
/* The relocation work is actually performed in SMM context, but the code
* resides in the ramstage module. This occurs by trampolining from the default
* SMRAM entry point to here. */
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase)
{
msr_t mtrr_cap;
struct smm_relocation_params *relo_params = &smm_reloc_params;
em64t101_smm_state_save_area_t *save_state;
u32 smbase = staggered_smbase;
u32 iedbase = relo_params->ied_base;
printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
/* Make appropriate changes to the save state map. */
printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
smbase, iedbase);
save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
sizeof(*save_state));
save_state->smbase = smbase;
save_state->iedbase = iedbase;
/* Write EMRR and SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED && !IS_ENABLED(CONFIG_HAS_NO_SMRR))
write_smrr(relo_params);
}
/*
* The default SMM entry can happen in parallel or serially. If the
* default SMM entry is done in parallel the BSP has already setup
* the saving state to each CPU's MSRs. At least one save state size
* is required for the initial SMM entry for the BSP to determine if
* parallel SMM relocation is even feasible.
*/
void smm_relocate(void)
{
/*
* If smm_save_state_in_msrs is non-zero then parallel SMM relocation
* shall take place. Run the relocation handler a second time on the
* BSP to do * the final move. For APs, a relocation handler always
* needs to be run.
*/
if (!boot_cpu())
smm_initiate_relocation();
}