sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/sandybridge: Add a chipset devicetree

Browse Source 
This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.

Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2021-08-11 13:42:40 +02:00
committed by Martin L Roth
parent 6cecb0d963
commit 691d58f999
43 changed files with 25 additions and 367 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/google/parrot/devicetree.cb
View File

@@ -19,18 +19,6 @@ chip northbridge/intel/sandybridge
register "max_mem_clock_mhz" = "666"
device cpu_cluster 0 on
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0 on end
device lapic 0xacac off end
register "acpi_c1" = "1" # ACPI(C1) = MWAIT(C1)
register "acpi_c2" = "3" # ACPI(C2) = MWAIT(C3)
register "acpi_c3" = "5" # ACPI(C3) = MWAIT(C7)
end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller