From 69353f409455c45bf8d39eb16b26995f50c24fa7 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Fri, 24 Feb 2023 15:15:01 -0700 Subject: [PATCH] Revert "rpl: Switch to S0iX" This reverts commit e0bf2e4691f1e8acb9c0700467b5735e108da318. --- src/mainboard/system76/rpl/Kconfig | 2 ++ src/mainboard/system76/rpl/devicetree.cb | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index e7c3b9a6cb..89ef54022a 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -6,6 +6,7 @@ config BOARD_SYSTEM76_RPL_COMMON select DRIVERS_INTEL_USB4_RETIMER select EC_SYSTEM76_EC select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT @@ -13,6 +14,7 @@ config BOARD_SYSTEM76_RPL_COMMON select MAINBOARD_HAS_TPM2 select MEMORY_MAPPED_TPM select NO_UART_ON_SUPERIO + select SOC_INTEL_ALDERLAKE_S3 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_COMMON_BLOCK_USB4 diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index 5a58beb7b6..2f6e15b852 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -11,8 +11,6 @@ chip soc/intel/alderlake # Enable Enhanced Intel SpeedStep register "eist_enable" = "1" - register "s0ix_enable" = "1" - # Enable C6 DRAM register "enable_c6dram" = "1"