soc/intel/xeon_sp: Use common P2SB functions to generate HPET DMAR

This makes coreboot more robust as it does not need to rely on syncing
values set by FSP and coreboot.

Change-Id: I2d954acdb939e7cb92d44b434ae628d7d935d776
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47533
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/xeon_sp/Kconfig

@@ -49,6 +49,7 @@ config	CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
 	select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_P2SB
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select SUPPORT_CPU_UCODE_IN_CBFS