soc/intel/common/block/cpu: Round up the number of ways

`CONFIG_DCACHE_RAM_SIZE' is not necessarily a multiple of way size. As
a result, when the `div' instruction is called to compute the needed
number of ways, there could be a remainder. When there is, one extra
way should be added to cover `CONFIG_DCACHE_RAM_SIZE'.

BUG=b:360332771
TEST=Verified on PTL Intel reference platform

Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83982
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/common/block/cpu/car/cache_as_ram.S

@@ -506,12 +506,20 @@ find_llc_subleaf:
 	jnc	set_eviction_mask
 
 	/*
-	 * RW data size / way size is equal to number of
+	 * round(RW data size / way size) is equal to number of
 	 * ways to be configured for non-eviction
 	 */
 	mov	$CONFIG_DCACHE_RAM_SIZE, %eax
 	xor	%edx, %edx /* Clear the upper 32-bit of dividend */
 	div	%ecx
+	/*
+	 * Increment data_ways by 1 if RW data size (CONFIG_DCACHE_RAM_SIZE) is
+	 * not divisible by way_size (ECX)
+	 */
+	movl	$0x01, %ecx
+	cmp	$0x00, %edx
+	cmovne	%ecx, %edx
+	add	%edx, %eax
 	mov	%eax, %edx /* back up data_ways in edx */
 	mov	%eax, %ecx
 	movl	$0x01, %eax