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The Errata350 is "Write 0000_8000h to register F2x[1, 0]9C_xD080F0C.", instead of

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F2x[1, 0]9C_x0C. It is a obvious bug. Some typos are also fixed.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao
2009-08-19 07:08:10 +00:00
committed by Zheng Bao
parent c5f3f19d0f
commit 69a031c4e1
1 changed files with 14 additions and 14 deletions
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28
src/northbridge/amd/amdmct/wrappers/mcti_d.c
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@@ -347,45 +347,45 @@ void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid); u32Addr = mct_GetRcvrSysAddr_D(pMCTstat, pDCTstat, u8Channel, u8Receiver, &u8Valid);
if(!u8Valid) { /* Address not supported on current CS */ if(!u8Valid) { /* Address not supported on current CS */
print_t("vErrara350: Address not supported on current CS\n"); print_t("vErrata350: Address not supported on current CS\n");
continue; continue;
} }
print_t("vErrara350: dummy read \n"); print_t("vErrata350: dummy read \n");
read32_fs(u32Addr); read32_fs(u32Addr);
} }
} }
print_t("vErrara350: step 2a\n"); print_t("vErrata350: step 2a\n");
/* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */ /* 2. Write 0000_8000h to register F2x[1, 0]9C_xD080F0C. */
u32DctDev = pDCTstat->dev_dct; u32DctDev = pDCTstat->dev_dct;
Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00008000); Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00008000);
/* ^--- value /* ^--- value
^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG.
^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
if(!pDCTstat->GangedMode) { if(!pDCTstat->GangedMode) {
print_t("vErrara350: step 2b\n"); print_t("vErrata350: step 2b\n");
Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00008000); Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00008000);
/* ^--- value /* ^--- value
^---F2x[1, 0]9C_x0C DRAM Phy Miscellaneous Register ^---F2x[1, 0]9C_x0D080F0C, No description in BKDG
^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */ ^----F2x[1, 0]98 DRAM Controller Additional Data Offset Register */
} }
print_t("vErrara350: step 3\n"); print_t("vErrata350: step 3\n");
/* 3. Wait at least 300 nanoseconds. */ /* 3. Wait at least 300 nanoseconds. */
coreDelay(); coreDelay();
print_t("vErrara350: step 4\n"); print_t("vErrata350: step 4\n");
/* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */ /* 4. Write 0000_0000h to register F2x[1, 0]9C_xD080F0C. */
Set_NB32_index_wait(u32DctDev, 0x098, 0x0c, 0x00000000); Set_NB32_index_wait(u32DctDev, 0x098, 0xD080F0C, 0x00000000);
if(!pDCTstat->GangedMode) { if(!pDCTstat->GangedMode) {
print_t("vErrara350: step 4b\n"); print_t("vErrata350: step 4b\n");
Set_NB32_index_wait(u32DctDev, 0x198, 0x0c, 0x00000000); Set_NB32_index_wait(u32DctDev, 0x198, 0xD080F0C, 0x00000000);
} }
print_t("vErrara350: step 5\n"); print_t("vErrata350: step 5\n");
/* 5. Wait at least 2 microseconds. */ /* 5. Wait at least 2 microseconds. */
coreDelay(); coreDelay();