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soc/amd/picasso,stoneyridge/acpi: use defines for MADT parameters

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Using existing defines instead of magic values improves readability of
the code. Also add comments to the MADT IRQ overrides to make it clearer
what those actually do.

TEST=Timeless build results in identical binary for amd/gardenia
(Stoneyridge), amd/mandolin (Picasso) and amd/majolica (Cezanne)

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I224ffbe8eb65bcdd5fc70c0ff8b15d55b3f6be01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55613
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
2021-06-17 15:48:25 +02:00
parent 21e4bd4e8c
commit 69a957f85c
3 changed files with 28 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/soc/amd/cezanne/acpi.c
View File

@ -31,19 +31,18 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS);
current += acpi_create_madt_irqoverride( /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */
(acpi_madt_irqoverride_t *)current, current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current,
MP_BUS_ISA, 0, 2, MP_BUS_ISA, 0, 2,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT); MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT);
current += acpi_create_madt_irqoverride( /* SCI IRQ type override */
(acpi_madt_irqoverride_t *)current, current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current,
MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ, MP_BUS_ISA, ACPI_SCI_IRQ, ACPI_SCI_IRQ,
MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
current = acpi_fill_madt_irqoverride(current); current = acpi_fill_madt_irqoverride(current);
/* create all subtables for processors */ /* create all subtables for processors */
current += acpi_create_madt_lapic_nmi( current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
(acpi_madt_lapic_nmi_t *)current,
ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS,
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
1 /* 1: LINT1 connect to NMI */); 1 /* 1: LINT1 connect to NMI */);

22
src/soc/amd/picasso/acpi.c
View File

@ -40,22 +40,22 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS); GNB_IOAPIC_ID, GNB_IO_APIC_ADDR, IO_APIC_INTERRUPTS);
/* 0: mean bus 0--->ISA */ /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */
/* 0: PIC 0 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current,
/* 2: APIC 2 */ MP_BUS_ISA, 0, 2,
/* 5 mean: 0101 --> Edge-triggered, Active high */ MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) /* SCI IRQ type override */
current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current,
current += acpi_create_madt_irqoverride( MP_BUS_ISA, 9, 9,
(acpi_madt_irqoverride_t *)current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
current = acpi_fill_madt_irqoverride(current); current = acpi_fill_madt_irqoverride(current);
/* create all subtables for processors */ /* create all subtables for processors */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
0xff, 5, 1); ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS,
/* 1: LINT1 connect to NMI */ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
1 /* 1: LINT1 connect to NMI */);
return current; return current;
} }

22
src/soc/amd/stoneyridge/acpi.c
View File

@ -10,6 +10,7 @@
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
@ -35,19 +36,20 @@ unsigned long acpi_fill_madt(unsigned long current)
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
GNB_IOAPIC_ID, IO_APIC2_ADDR, 24); GNB_IOAPIC_ID, IO_APIC2_ADDR, 24);
/* 0: mean bus 0--->ISA */ /* PIT is connected to legacy IRQ 0, but IOAPIC GSI 2 */
/* 0: PIC 0 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current,
/* 2: APIC 2 */ MP_BUS_ISA, 0, 2,
/* 5 mean: 0101 --> Edge-triggered, Active high */ MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) /* SCI IRQ type override */
current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current,
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) MP_BUS_ISA, 9, 9,
current, 0, 9, 9, 0xf); MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
/* create all subtables for processors */ /* create all subtables for processors */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
0xff, 5, 1); ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS,
/* 1: LINT1 connect to NMI */ MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
1 /* 1: LINT1 connect to NMI */);
return current; return current;
} }