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Google Link: Add remaining code to support native graphics

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The Link native graphics commit 49428d84 [1]

    Add support for Google's Chromebook Pixel

was missing some of the higher level bits, and hence could not be
used.  This is not new code -- it has been working since last
August -- so the effort now is to get it into the tree and structure
it in a way compatible with upstream coreboot.

1. Add options to src/device/Kconfig to enable native graphics.
2. Export the MTRR function for setting variable MTRRs.
3. Clean up some of the comments and white space.

While I realize that the product name is Pixel, the mainboard in the
coreboot tree is called Link, and that name is what we will use
in our commits.

[1] http://review.coreboot.org/2482

Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2531
Tested-by: build bot (Jenkins)
This commit is contained in:
Ronald G. Minnich
2013-02-26 10:07:40 -08:00
parent 26855fc70b
commit 69efaa0388
5 changed files with 73 additions and 17 deletions
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47
src/northbridge/intel/sandybridge/gma.c
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@@ -23,6 +23,9 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include "chip.h"
#include "sandybridge.h"
@@ -619,20 +622,47 @@ static void gma_pm_init_post_vbios(struct device *dev)
static void gma_func0_init(struct device *dev)
{
u32 reg32;
u32 graphics_base, graphics_size;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Set up an MTRR for the graphics memory BAR to vastly improve
* speed of VGA initialization (and later access). To stay out of
* the way of the MTRR init code, we are using MTRR #8 to cover
* that range.
*/
graphics_base = dev->resource_list[1].base;
graphics_size = dev->resource_list[1].size;
printk(BIOS_DEBUG, "Setting up MTRR for graphics 0x%08x (%dK)\n",
graphics_base, graphics_size / 1024);
set_var_mtrr(8, graphics_base >> 10, graphics_size >> 10,
MTRR_TYPE_WRCOMB, 0x24);
/* Init graphics power management */
gma_pm_init_pre_vbios(dev);
#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
#endif
/* Post VBIOS init */
gma_pm_init_post_vbios(dev);
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* This should probably run before post VBIOS init. */
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
u32 iobase, mmiobase, physbase;
iobase = dev->resource_list[2].base;
mmiobase = dev->resource_list[0].base;
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
i915lightup(physbase, iobase, mmiobase, graphics_base);
#endif
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -660,12 +690,13 @@ static struct device_operations gma_func0_ops = {
.ops_pci = &gma_pci_ops,
};
static const unsigned short gma_ids[] = {
0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, 0x166,
0,
};
static const struct pci_driver gma_gt1_desktop __pci_driver = {
.ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices= gma_ids,
static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112,
0x0116, 0x0122, 0x0126, 0x0156,
0x0166,
0 };
static const struct pci_driver gma __pci_driver = {
.ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};