Initial support for the Intel 82830 northbridge and RCA RM4100 board.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith
committed by
Uwe Hermann
Uwe Hermann
parent
c4f5365688
commit
6a1dc86005
508
src/northbridge/intel/i82830/raminit.c
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508
src/northbridge/intel/i82830/raminit.c
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@@ -0,0 +1,508 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include <spd.h>
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#include <sdram_mode.h>
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#include <delay.h>
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#include "debug.c"
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#include "i82830.h"
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/*-----------------------------------------------------------------------------
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Macros and definitions.
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-----------------------------------------------------------------------------*/
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/* Uncomment this to enable debugging output. */
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/* #define DEBUG_RAM_SETUP 1 */
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/* Debugging macros. */
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#if defined(DEBUG_RAM_SETUP)
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#define PRINT_DEBUG(x) print_debug(x)
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#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
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#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
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#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
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#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
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#else
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#define PRINT_DEBUG(x)
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#define PRINT_DEBUG_HEX8(x)
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#define PRINT_DEBUG_HEX16(x)
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#define PRINT_DEBUG_HEX32(x)
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#define DUMPNORTH()
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#endif
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/* DRC[10:8] - Refresh Mode Select (RMS).
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* 0x0 for Refresh Disabled (Self Refresh)
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* 0x1 for Refresh interval 15.6 us for 133MHz
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* 0x2 for Refresh interval 7.8 us for 133MHz
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* 0x7 /* Refresh interval 128 Clocks. (Fast Refresh Mode)
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*/
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#define RAM_COMMAND_REFRESH 0x2
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/* DRC[6:4] - SDRAM Mode Select (SMS). */
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#define RAM_COMMAND_SELF_REFRESH 0x0
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#define RAM_COMMAND_NOP 0x1
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#define RAM_COMMAND_PRECHARGE 0x2
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#define RAM_COMMAND_MRS 0x3
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#define RAM_COMMAND_CBR 0x6
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#define RAM_COMMAND_NORMAL 0x7
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/* DRC[29] - Initialization Complete (IC). */
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#define RAM_COMMAND_IC 0x1
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/*-----------------------------------------------------------------------------
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SDRAM configuration functions.
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-----------------------------------------------------------------------------*/
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/* Send the specified RAM command to all DIMMs. */
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static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
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uint32_t addr_offset)
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{
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int i;
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uint8_t reg8, reg8_2 = 0;
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uint32_t reg32;
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/* Configure the RAM command. */
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reg32 = pci_read_config32(ctrl->d0, DRC);
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/* Clear bits 29, 10-8, 6-4. */
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reg32 &= 0xdffff88f;
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reg32 |= command << 4;
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/* If RAM_COMMAND_NORMAL set the refresh mode and IC bit. */
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if (command == RAM_COMMAND_NORMAL)
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reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29));
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pci_write_config32(ctrl->d0, DRC, reg32);
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/* RAM_COMMAND_NORMAL affects only the memory controller and
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doesn't need to be "sent" to the DIMMs. */
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/* if (command == RAM_COMMAND_NORMAL) return; */
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PRINT_DEBUG(" Sending RAM command 0x");
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PRINT_DEBUG_HEX32(reg32);
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PRINT_DEBUG(" to 0x");
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PRINT_DEBUG_HEX32(0 + addr_offset);
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PRINT_DEBUG("\r\n");
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/* NOTE: Dual-sided ready. */
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read32(0 + addr_offset);
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for (i = 0; i < 4; i++) {
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reg8 = pci_read_config8(ctrl->d0, DRB + i);
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if (reg8 != reg8_2)
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read32(reg8 * 32 * 1024 * 1024);
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reg8_2 = reg8;
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}
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}
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/*-----------------------------------------------------------------------------
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DIMM-independant configuration functions.
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-----------------------------------------------------------------------------*/
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struct dimm_size {
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unsigned long side1;
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unsigned long side2;
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};
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static struct dimm_size spd_get_dimm_size(unsigned device)
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{
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struct dimm_size sz;
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int i, module_density, dimm_banks;
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sz.side1 = 0;
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module_density = spd_read_byte(device, 31);
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dimm_banks = spd_read_byte(device, 5);
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/* Find the size of side1. */
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/* Find the larger value. The larger value is always side1. */
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for (i = 512; i >= 0; i >>= 1) {
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if ((module_density & i) == i) {
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sz.side1 = i;
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break;
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}
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}
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/* Set to 0 in case it's single sided. */
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sz.side2 = 0;
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/* Test if it's a dual-sided DIMM. */
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if (dimm_banks > 1) {
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/* Test to see if there's a second value, if so it's asymmetrical. */
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if (module_density != i) {
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/* Find the second value, picking up where we left off. */
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/* i >>= 1 done initially to make sure we don't get the same value again. */
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for (i >>= 1; i >= 0; i >>= 1) {
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if (module_density == (sz.side1 | i)) {
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sz.side2 = i;
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break;
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}
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}
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/* If not, it's symmetrical */
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} else {
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sz.side2 = sz.side1;
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}
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}
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/* SPD byte 31 is the memory size divided by 4 so we
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* need to muliply by 4 to get the total size.
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*/
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sz.side1 *= 4;
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sz.side2 *= 4;
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return sz;
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}
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static void spd_set_dram_size(const struct mem_controller *ctrl)
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{
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int i, value, drb1, drb2;
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for (i = 0; i < DIMM_SOCKETS; i++) {
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struct dimm_size sz;
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unsigned device;
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device = ctrl->channel0[i];
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drb1 = 0;
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drb2 = 0;
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/* First check if a DIMM is actually present. */
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if (spd_read_byte(device, 2) == 0x4) {
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print_debug("Found DIMM in slot ");
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print_debug_hex8(i);
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print_debug("\r\n");
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sz = spd_get_dimm_size(device);
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/* WISHLIST: would be nice to display it as decimal? */
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print_debug("DIMM is 0x");
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print_debug_hex16(sz.side1);
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print_debug(" on side 1\r\n");
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print_debug("DIMM is 0x");
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print_debug_hex16(sz.side2);
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print_debug(" on side 2\r\n");
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/* Test for PC133 (i82830 only supports PC133) */
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/* PC133 SPD9 - cycle time is always 75 */
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if (spd_read_byte(device, 9) != 0x75) {
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print_err("SPD9 DIMM Is Not PC133 Compatable\r\n");
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die("HALT\r\n");
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}
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/* PC133 SPD10 - access time is always 54 */
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if (spd_read_byte(device, 10) != 0x54) {
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print_err("SPD10 DIMM Is Not PC133 Compatable\r\n");
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die("HALT\r\n");
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}
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/* The i82830 only supports a symmetrical dual-sided dimms
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* and can't handle DIMMs smaller than 32MB per
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* side or larger than 256MB per side.
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*/
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if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
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print_err("This northbridge only supports\r\n");
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print_err("symmetrical dual-sided DIMMs\r\n");
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print_err("booting as a single-sided DIMM\r\n");
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sz.side2 = 0;
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}
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if ((sz.side1 < 32)) {
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print_err("DIMMs smaller than 32MB per side\r\n");
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print_err("are not supported on this northbridge\r\n");
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die("HALT\r\n");
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}
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if ((sz.side1 > 256)) {
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print_err
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("DIMMs larger than 256MB per side\r\n");
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print_err
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("are not supported on this northbridge\r\n");
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die("HALT\r\n");
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}
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/* We need to divide size by 32 to set up the
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* DRB registers.
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*/
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if (sz.side1)
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drb1 = sz.side1 / 32;
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if (sz.side2)
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drb2 = sz.side2 / 32;
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} else {
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PRINT_DEBUG("No DIMM found in slot ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG("\r\n");
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/* If there's no DIMM in the slot, set value to 0. */
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drb1 = 0;
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drb2 = 0;
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}
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/* Set the value for DRAM Row Boundary Registers */
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if (i == 0) {
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pci_write_config8(ctrl->d0, DRB, drb1);
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pci_write_config8(ctrl->d0, DRB + 1, drb1 + drb2);
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PRINT_DEBUG("DRB 0x");
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PRINT_DEBUG_HEX8(DRB);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(drb1);
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PRINT_DEBUG("\r\n");
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PRINT_DEBUG("DRB1 0x");
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PRINT_DEBUG_HEX8(DRB + 1);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(drb1 + drb2);
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PRINT_DEBUG("\r\n");
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} else if (i == 1) {
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value = pci_read_config8(ctrl->d0, DRB + 1);
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pci_write_config8(ctrl->d0, DRB + 2, value + drb1);
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pci_write_config8(ctrl->d0, DRB + 3,
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value + drb1 + drb2);
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PRINT_DEBUG("DRB2 0x");
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PRINT_DEBUG_HEX8(DRB + 2);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(value + drb1);
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PRINT_DEBUG("\r\n");
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PRINT_DEBUG("DRB3 0x");
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PRINT_DEBUG_HEX8(DRB + 3);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(value + drb1 + drb2);
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PRINT_DEBUG("\r\n");
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/* We need to set the highest DRB value to 0x64 and 0x65.
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* These are supposed to be "Reserved" but memory will
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* not initialize properly if we don't.
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*/
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value = pci_read_config8(ctrl->d0, DRB + 3);
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pci_write_config8(ctrl->d0, DRB + 4, value);
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pci_write_config8(ctrl->d0, DRB + 5, value);
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}
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}
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}
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static void set_dram_row_attributes(const struct mem_controller *ctrl)
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{
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int i, dra, col, width, value;
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for (i = 0; i < DIMM_SOCKETS; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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/* First check if a DIMM is actually present. */
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if (spd_read_byte(device, 2) == 0x4) {
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print_debug("Found DIMM in slot ");
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print_debug_hex8(i);
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print_debug(", setting DRA...\r\n");
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dra = 0x00;
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/* columns */
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col = spd_read_byte(device, 4);
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/* data width */
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width = spd_read_byte(device, 6);
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/* calculate page size in bits */
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value = ((1 << col) * width);
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/* convert to Kilobytes */
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dra = ((value / 8) >> 10);
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/* # of banks of DIMM (single or double sided) */
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value = spd_read_byte(device, 5);
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if (value == 1) {
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switch (dra) {
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case 2: /* 2KB */
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dra = 0xF0;
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break;
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case 4: /* 4KB */
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dra = 0xF1;
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break;
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case 8: /* 8KB */
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dra = 0xF2;
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break;
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case 16: /* 16KB */
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dra = 0xF3;
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break;
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default:
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print_err("Page size not supported\r\n");
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die("HALT\r\n");
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}
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} else if (value == 2) {
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switch (dra) {
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case 2: /* 2KB */
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dra = 0x00;
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break;
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case 4: /* 4KB */
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dra = 0x11;
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break;
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case 8: /* 8KB */
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dra = 0x22;
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break;
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case 16: /* 16KB */
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dra = 0x33;
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break;
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default:
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print_err("Page size not supported\r\n");
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die("HALT\r\n");
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}
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} else {
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print_err("# of banks of DIMM not supported\r\n");
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die("HALT\r\n");
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}
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} else {
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PRINT_DEBUG("No DIMM found in slot ");
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PRINT_DEBUG_HEX8(i);
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PRINT_DEBUG(", setting DRA to 0xFF\r\n");
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/* If there's no DIMM in the slot, set dra value to 0xFF. */
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dra = 0xFF;
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}
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/* Set the value for DRAM Row Attribute Registers */
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pci_write_config8(ctrl->d0, DRA + i, dra);
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PRINT_DEBUG("DRA 0x");
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PRINT_DEBUG_HEX8(DRA + i);
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PRINT_DEBUG(" has been set to 0x");
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PRINT_DEBUG_HEX8(dra);
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PRINT_DEBUG("\r\n");
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}
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}
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static void set_dram_timing(const struct mem_controller *ctrl)
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{
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/* Set the value for DRAM Timing Register */
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/* TODO: Configure the value according to SPD values. */
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pci_write_config32(ctrl->d0, DRT, 0x00000010);
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}
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static void set_dram_buffer_strength(const struct mem_controller *ctrl)
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{
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/* TODO: This needs to be set according to the DRAM tech
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* (x8, x16, or x32). Argh, Intel provides no docs on this!
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* Currently, it needs to be pulled from the output of
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* lspci -xxx Rx92
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*/
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/* Set the value for System Memory Buffer Strength Control Registers */
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pci_write_config32(ctrl->d0, BUFF_SC, 0xFC9B491B);
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}
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/*-----------------------------------------------------------------------------
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Public interface.
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-----------------------------------------------------------------------------*/
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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uint16_t value;
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int igd_memory = 0;
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PRINT_DEBUG("Setting initial registers....\r\n");
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/* Set the value for GMCH Control Register #0 */
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pci_write_config16(ctrl->d0, GCC0, 0xA072);
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/* Set the value for GMCH Control Register #1 */
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switch (CONFIG_VIDEO_MB) {
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case 512: /* 512K of memory */
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igd_memory = 0x2;
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break;
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case 1: /* 1M of memory */
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igd_memory = 0x3;
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break;
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case 8: /* 8M of memory */
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igd_memory = 0x4;
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break;
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default: /* No memory */
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pci_write_config16(ctrl->d0, GCC1, 0x0002);
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igd_memory = 0x0;
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}
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value = pci_read_config16(ctrl->d0, GCC1);
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value |= igd_memory << 4;
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pci_write_config16(ctrl->d0, GCC1, value);
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/* Set the value for Aperture Base Configuration Register */
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pci_write_config32(ctrl->d0, APBASE, 0x00000008);
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/* Set the value for Register Range Base Address Register */
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pci_write_config32(ctrl->d0, RRBAR, 0x00000000);
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/* Set the value for Fixed DRAM Hole Control Register */
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pci_write_config8(ctrl->d0, FDHC, 0x00);
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/* Set the value for Programable Attribute Map Registers
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* Ideally, this should be R/W for as many ranges as possible.
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*/
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pci_write_config8(ctrl->d0, PAM0, 0x30);
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pci_write_config8(ctrl->d0, PAM1, 0x33);
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pci_write_config8(ctrl->d0, PAM2, 0x33);
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pci_write_config8(ctrl->d0, PAM3, 0x33);
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pci_write_config8(ctrl->d0, PAM4, 0x33);
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pci_write_config8(ctrl->d0, PAM5, 0x33);
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pci_write_config8(ctrl->d0, PAM6, 0x33);
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/* Set the value for DRAM Throttling Control Register */
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pci_write_config32(ctrl->d0, DTC, 0x00000000);
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||||
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||||
/* Set the value for System Management RAM Control Register */
|
||||
pci_write_config8(ctrl->d0, SMRAM, 0x02);
|
||||
|
||||
/* Set the value for Extended System Management RAM Control Register */
|
||||
pci_write_config8(ctrl->d0, ESMRAMC, 0x38);
|
||||
|
||||
PRINT_DEBUG("Initial registers have been set.\r\n");
|
||||
}
|
||||
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
||||
{
|
||||
spd_set_dram_size(ctrl);
|
||||
set_dram_row_attributes(ctrl);
|
||||
set_dram_timing(ctrl);
|
||||
set_dram_buffer_strength(ctrl);
|
||||
}
|
||||
|
||||
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* 0. Wait until power/voltages and clocks are stable (200us). */
|
||||
udelay(200);
|
||||
|
||||
/* 1. Apply NOP. */
|
||||
PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
|
||||
do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
|
||||
udelay(200);
|
||||
|
||||
/* 2. Precharge all. Wait tRP. */
|
||||
PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
|
||||
do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
|
||||
udelay(1);
|
||||
|
||||
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
|
||||
PRINT_DEBUG("RAM Enable 3: CBR\r\n");
|
||||
for (i = 0; i < 8; i++) {
|
||||
do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
/* 4. Mode register set. Wait two memory cycles. */
|
||||
/* TODO: Set offset according to DRT values */
|
||||
PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
|
||||
do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
|
||||
udelay(2);
|
||||
|
||||
/* 5. Normal operation (enables refresh) */
|
||||
PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
|
||||
do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
|
||||
udelay(1);
|
||||
|
||||
PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
|
||||
DUMPNORTH();
|
||||
}
|
||||
Reference in New Issue
Block a user