mb/google/brya/var/nova: Add SOLDERDOWN support

Nova will use SOLDERDOWN. Add memory.c to override baseboard.
Update dram id table for correct platform parameter.

BUG=b:328711879

Change-Id: I6fbce991ef5ab9f0e6216ad1a5af73fcc1996a2a
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82474
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/Kconfig

@@ -67,7 +67,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
 	select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG
 	select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
 	select HAVE_SLP_S0_GATE
-	select MEMORY_SODIMM if !BOARD_GOOGLE_CONSTITUTION
+	select MEMORY_SODIMM if !(BOARD_GOOGLE_CONSTITUTION || BOARD_GOOGLE_NOVA)
 	select RT8168_GEN_ACPI_POWER_RESOURCE
 	select RT8168_GET_MAC_FROM_VPD
 	select RT8168_SET_LED_MODE
@@ -362,6 +362,7 @@ config BOARD_GOOGLE_NOKRIS
 config BOARD_GOOGLE_NOVA
 	select BOARD_GOOGLE_BASEBOARD_BRASK
 	select SOC_INTEL_RAPTORLAKE
+	select MEMORY_SOLDERDOWN
 
 config BOARD_GOOGLE_OMNIGUL
 	select BOARD_GOOGLE_BASEBOARD_BRYA

src/mainboard/google/brya/variants/nova/Makefile.mk

@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c

src/mainboard/google/brya/variants/nova/memory.c

@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+
+static const struct mb_cfg baseboard_memcfg = {
+	.type = MEM_TYPE_LP4X,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {40, 30, 30, 30, 30},
+	},
+
+	/* DQ byte map as per doc #573387 */
+	.lpx_dq_map = {
+		.ddr0 = {
+			.dq0 = {  3,  0,  2,  1,  4,  6,  5,  7, },
+			.dq1 = {  12, 13, 14, 15, 8,  9,  10, 11, },
+		},
+		.ddr1 = {
+			.dq0 = { 13, 14, 11, 12,  10, 8, 15,  9, },
+			.dq1 = {  5,  2,  4,  3,  1,  6,  0,  7, },
+		},
+		.ddr2 = {
+			.dq0 = {  2,  3,  1,  0,  7,  6,  5,  4, },
+			.dq1 = { 12,  13, 14, 15, 8,  9, 10, 11, },
+		},
+		.ddr3 = {
+			.dq0 = { 13, 14, 12, 15, 11,  9,  8, 10, },
+			.dq1 = {  5,  2,  1,  4,  7,  0,  3,  6, },
+		},
+		.ddr4 = {
+			.dq0 = { 11, 10,  8,  9, 14, 15, 13, 12, },
+			.dq1 = {  3,  0,  2,  1,  5,  4,  6,  7, },
+		},
+		.ddr5 = {
+			.dq0 = { 11, 15, 13, 12, 10,  9, 14,  8, },
+			.dq1 = {  3,  0,  2,  1,  6,  7,  5,  4, },
+		},
+		.ddr6 = {
+			.dq0 = { 11, 13, 10, 12, 15,  9, 14,  8, },
+			.dq1 = {  4,  3,  5,  2,  7,  0,  1,  6, },
+		},
+		.ddr7 = {
+			.dq0 = { 12, 13, 15, 14, 11,  9, 10,  8, },
+			.dq1 = {  4,  5,  1,  2,  6,  3,  0,  7, },
+		},
+	},
+
+	/* DQS CPU<>DRAM map as per doc #573387 */
+	.lpx_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+		.ddr7 = { .dqs0 = 1, .dqs1 = 0 },
+	},
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ect = 1, /* Enable Early Command Training */
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &baseboard_memcfg;
+}
+
+int variant_memory_sku(void)
+{
+	/*
+	 * Memory configuration board straps
+	 * GPIO_MEM_CONFIG_0	GPP_F16
+	 * GPIO_MEM_CONFIG_1	GPP_F12
+	 * GPIO_MEM_CONFIG_2	GPP_F13
+	 * GPIO_MEM_CONFIG_3	GPP_F15
+	 */
+	gpio_t spd_gpios[] = {
+		GPP_F16,
+		GPP_F12,
+		GPP_F13,
+		GPP_F15,
+	};
+
+	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+bool variant_is_half_populated(void)
+{
+	/* GPIO_MEM_CH_SEL GPP_F11 */
+	return gpio_get(GPP_F11);
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}

src/mainboard/google/brya/variants/nova/memory/Makefile.mk

@@ -1,8 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
 
 SPD_SOURCES =
-SPD_SOURCES += spd/lp4x/set-1/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE
+SPD_SOURCES += spd/lp4x/set-0/spd-1.hex      # ID = 0(0b0000)  Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE
-SPD_SOURCES += spd/lp4x/set-1/spd-3.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL

src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt

@@ -1,10 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 # This is an auto-generated file. Do not edit!!
 # Generated by:
-# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
+# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt
 
 DRAM Part Name                 ID to assign
 K4U6E3S4AB-MGCL                0 (0000)
 H9HCNNNBKMMLXR-NEE             0 (0000)
-MT53E1G32D2NP-046 WT:B         1 (0001)
-K4UBE3D4AB-MGCL                1 (0001)

src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt

@@ -1,4 +1,2 @@
 K4U6E3S4AB-MGCL
 H9HCNNNBKMMLXR-NEE
-MT53E1G32D2NP-046 WT:B
-K4UBE3D4AB-MGCL