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src/include: Wrap lines at 80 columns

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Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

Changed a few comments to reduce line length.  File
src/include/cpu/amd/vr.h was skipped.

TEST=Build and run on Galileo Gen2

Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18687
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
2017-03-07 17:45:12 -08:00
parent d0f26fcea2
commit 6a566d7fbe
37 changed files with 468 additions and 249 deletions
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6
src/include/cpu/amd/amdfam10_sysconf.h
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@@ -40,7 +40,8 @@ struct amdfam10_sysconf_t {
unsigned int nodes;
unsigned int ht_c_num; // we only can have 32 ht chain at most
unsigned int ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable
// 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable
unsigned int ht_c_conf_bus[HC_NUMS];
unsigned int io_addr_num;
unsigned int conf_io_addr[HC_NUMS];
unsigned int conf_io_addrx[HC_NUMS];
@@ -50,7 +51,8 @@ struct amdfam10_sysconf_t {
unsigned int segbit;
unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234
msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5
// quad cores all cores in one node should be the same, and p0,..p5
msr_t msr_pstate[NODE_NUMS * 5];
unsigned int needs_update_pstate_msrs;
unsigned int bsp_apicid;