sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/include: Wrap lines at 80 columns

Browse Source 
Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

Changed a few comments to reduce line length.  File
src/include/cpu/amd/vr.h was skipped.

TEST=Build and run on Galileo Gen2

Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18687
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
2017-03-07 17:45:12 -08:00
parent d0f26fcea2
commit 6a566d7fbe
37 changed files with 468 additions and 249 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
src/include/spd_ddr2.h
View File

@ -54,7 +54,9 @@
SDRAM device, it could be 0x4, 0x8, so address
lines for that would be 2, and 3 */
/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planr), Height bit[7:5] */
/* Number of Ranks bit [2:0], Package (bit4, 1 = stack, 0 = planr),
* Height bit[7:5]
*/
#define SPD_MOD_ATTRIB_RANK 5
#define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0
#define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07
@ -72,9 +74,12 @@
#define SPD_RANK_SIZE_256MB (1<<6)
#define SPD_RANK_SIZE_512MB (1<<7)
#define SPD_DATA_WIDTH 6 /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */
#define SPD_PRI_WIDTH 13 /* Primary SDRAM Width, it could be 0x08 or 0x10 */
#define SPD_ERR_WIDTH 14 /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */
/* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */
#define SPD_DATA_WIDTH 6
/* Primary SDRAM Width, it could be 0x08 or 0x10 */
#define SPD_PRI_WIDTH 13
/* Error Checking SDRAM Width, it could be 0x08 or 0x10 */
#define SPD_ERR_WIDTH 14
#define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */
#define SPD_CAS_LAT_2 (1<<2)
@ -84,16 +89,25 @@
#define SPD_CAS_LAT_6 (1<<6)
#define SPD_CAS_LAT_7 (1<<7)
#define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */
/* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2)
* + (val & 3) * 0.25)ns
*/
#define SPD_TRP 27
#define SPD_TRRD 28
#define SPD_TRCD 29
#define SPD_TRAS 30
#define SPD_TWR 36 /* x */
#define SPD_TWR 36 /* x */
#define SPD_TWTR 37 /* x */
#define SPD_TRTP 38 /* x */
#define SPD_EX_TRC_TRFC 40
#define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/
#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/
/* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)]
* ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}
*/
#define SPD_TRC 41
/* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)]
* + (val40 & 1)*256
*/
#define SPD_TRFC 42
#define SPD_TREF 12