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mb/google/zork: Drop redundant romstage GPIO table

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Now that the power and reset GPIO configuration for non-PCIe devices is
dropped from romstage GPIO table, the tables for pre-v3 and v3 version of
schematics are exactly same. So, this change drops the duplicate table and
also removes the check for v3 schematics when configuring the pads in
romstage.

BUG=b:154351731

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh
2020-07-14 16:08:20 -07:00
committed by Aaron Durbin
parent ddfec569d1
commit 6a5c77cc84
2 changed files with 6 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
View File

@@ -9,22 +9,7 @@
#include <boardid.h> #include <boardid.h>
#include <variant/gpio.h> #include <variant/gpio.h>
static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { static const struct soc_amd_gpio gpio_set_stage_rom[] = {
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH),
/* CLK_REQ0_L - WIFI */
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
/* CLK_REQ1_L - SD Card */
PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
/* CLK_REQ2_L - NVMe */
PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
/* SD_AUX_RESET_L */
PAD_GPO(GPIO_142, HIGH),
};
static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
/* PCIE_RST1_L - Variable timings (May remove) */ /* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* NVME_AUX_RESET_L */ /* NVME_AUX_RESET_L */
@@ -157,13 +142,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
const __weak const __weak
struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size) struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
{ {
if (variant_uses_v3_schematics()) { *size = ARRAY_SIZE(gpio_set_stage_rom);
*size = ARRAY_SIZE(gpio_set_stage_rom_v3); return gpio_set_stage_rom;
return gpio_set_stage_rom_v3;
}
*size = ARRAY_SIZE(gpio_set_stage_rom_pre_v3);
return gpio_set_stage_rom_pre_v3;
} }
const __weak const __weak

24
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
View File

@@ -9,20 +9,7 @@
#include <boardid.h> #include <boardid.h>
#include <variant/gpio.h> #include <variant/gpio.h>
static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = { static const struct soc_amd_gpio gpio_set_stage_rom[] = {
/* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH),
/* CLK_REQ0_L - WIFI */
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
/* CLK_REQ1_L - SD Card */
PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
/* CLK_REQ4_L - SSD */
PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
/* SD_AUX_RESET_L */
PAD_GPO(GPIO_142, HIGH),
};
static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
/* NVME_AUX_RESET_L */ /* NVME_AUX_RESET_L */
PAD_GPO(GPIO_40, HIGH), PAD_GPO(GPIO_40, HIGH),
/* CLK_REQ0_L - WIFI */ /* CLK_REQ0_L - WIFI */
@@ -151,13 +138,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
const __weak const __weak
struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size) struct soc_amd_gpio *variant_romstage_gpio_table(size_t *size)
{ {
if (variant_uses_v3_schematics()) { *size = ARRAY_SIZE(gpio_set_stage_rom);
*size = ARRAY_SIZE(gpio_set_stage_rom_v3); return gpio_set_stage_rom;
return gpio_set_stage_rom_v3;
}
*size = ARRAY_SIZE(gpio_set_stage_rom_pre_v3);
return gpio_set_stage_rom_pre_v3;
} }
const __weak const __weak