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cpu/intel/car: Prepare for some POSTCAR_STAGE support

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The file cache_as_ram_ht.inc is used across a variety
of CPUs and northbridges. We need to split it anyway
for future C_ENVIRONMENT_BOOTBLOCK and verstage work.

Split and rename the files, remove code that is globally
implemented in POSTCAR_STAGE framework already.

Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2018-05-17 17:22:51 +03:00
parent 8168046432
commit 6a8ce0d250
8 changed files with 449 additions and 5 deletions
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5
src/cpu/intel/socket_FCBGA559/Makefile.inc
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@@ -8,5 +8,10 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
else
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S
endif
romstage-y += ../car/romstage.c