soc/intel/skylake: Add config for enabling PCIe AER

Add a config for enabling/disabling Advanced Error Reporting feature
for PCIe root ports.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/skylake/chip.h

@@ -173,6 +173,7 @@ struct soc_intel_skylake_config {
 	u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
 	u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
 	u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
+	u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
 
 	/* USB related */
 	struct usb2_port_config usb2_ports[16];