soc/amd/stoneyridge: Move LPC support to common
AMD devices traditionally have the LPC-ISA bus at 14.3 and the definition has been very consistent. Relocate the feature from stoneyridge into common/block. BUG=b:131682806 Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson
committed by
Martin Roth
Martin Roth
parent
eceaa97b27
commit
6ab5ed3b66
@ -27,6 +27,7 @@
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/reset.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/lpc.h>
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#include <soc/southbridge.h>
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#include <soc/smbus.h>
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#include <soc/smi.h>
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@ -152,130 +153,12 @@ const static struct irq_idx_name irq_association[] = {
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{ PIRQ_UART1, "UART1" },
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};
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/*
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* Structure to simplify code obtaining the total of used wide IO
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* registers and the size assigned to each.
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*/
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static struct wide_io_ioport_and_bits {
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uint32_t enable;
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uint16_t port;
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uint8_t alt;
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} wio_io_en[TOTAL_WIDEIO_PORTS] = {
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{
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LPC_WIDEIO0_ENABLE,
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LPC_WIDEIO_GENERIC_PORT,
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LPC_ALT_WIDEIO0_ENABLE
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},
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{
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LPC_WIDEIO1_ENABLE,
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LPC_WIDEIO1_GENERIC_PORT,
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LPC_ALT_WIDEIO1_ENABLE
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},
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{
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LPC_WIDEIO2_ENABLE,
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LPC_WIDEIO2_GENERIC_PORT,
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LPC_ALT_WIDEIO2_ENABLE
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}
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};
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const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
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{
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*size = ARRAY_SIZE(irq_association);
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return irq_association;
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}
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/**
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* @brief Find the size of a particular wide IO
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*
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* @param index = index of desired wide IO
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*
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* @return size of desired wide IO
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*/
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uint16_t sb_wideio_size(int index)
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{
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uint32_t enable_register;
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uint16_t size = 0;
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uint8_t alternate_register;
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if (index >= TOTAL_WIDEIO_PORTS)
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return size;
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enable_register = pci_read_config32(SOC_LPC_DEV,
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LPC_IO_OR_MEM_DECODE_ENABLE);
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alternate_register = pci_read_config8(SOC_LPC_DEV,
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LPC_ALT_WIDEIO_RANGE_ENABLE);
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if (enable_register & wio_io_en[index].enable)
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size = (alternate_register & wio_io_en[index].alt) ?
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16 : 512;
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return size;
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}
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/**
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* @brief Identify if any LPC wide IO is covering the IO range
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*
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* @param start = start of IO range
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* @param size = size of IO range
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*
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* @return Index of wide IO covering the range or error
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*/
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int sb_find_wideio_range(uint16_t start, uint16_t size)
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{
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int i, index = WIDEIO_RANGE_ERROR;
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uint16_t end, current_size, start_wideio, end_wideio;
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end = start + size;
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for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) {
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current_size = sb_wideio_size(i);
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if (current_size == 0)
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continue;
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start_wideio = pci_read_config16(SOC_LPC_DEV,
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wio_io_en[i].port);
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end_wideio = start_wideio + current_size;
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if ((start >= start_wideio) && (end <= end_wideio)) {
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index = i;
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break;
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}
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}
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return index;
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}
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/**
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* @brief Program a LPC wide IO to support an IO range
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*
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* @param start = start of range to be routed through wide IO
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* @param size = size of range to be routed through wide IO
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*
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* @return Index of wide IO register used or error
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*/
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int sb_set_wideio_range(uint16_t start, uint16_t size)
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{
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int i, index = WIDEIO_RANGE_ERROR;
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uint32_t enable_register;
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uint8_t alternate_register;
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enable_register = pci_read_config32(SOC_LPC_DEV,
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LPC_IO_OR_MEM_DECODE_ENABLE);
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alternate_register = pci_read_config8(SOC_LPC_DEV,
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LPC_ALT_WIDEIO_RANGE_ENABLE);
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for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) {
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if (enable_register & wio_io_en[i].enable)
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continue;
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index = i;
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pci_write_config16(SOC_LPC_DEV, wio_io_en[i].port, start);
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enable_register |= wio_io_en[i].enable;
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pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE,
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enable_register);
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if (size <= 16)
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alternate_register |= wio_io_en[i].alt;
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else
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alternate_register &= ~wio_io_en[i].alt;
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pci_write_config8(SOC_LPC_DEV,
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LPC_ALT_WIDEIO_RANGE_ENABLE,
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alternate_register);
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break;
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}
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return index;
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}
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static void power_on_aoac_device(int aoac_device_control_register)
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{
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uint8_t byte;
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@ -315,16 +198,7 @@ void enable_aoac_devices(void)
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} while (!status);
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}
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void sb_pci_port80(void)
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{
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u8 byte;
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byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
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byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */
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pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
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}
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void sb_lpc_port80(void)
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static void sb_enable_lpc(void)
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{
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u8 byte;
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@ -332,14 +206,9 @@ void sb_lpc_port80(void)
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byte = pm_io_read8(PM_LPC_GATING);
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byte |= PM_LPC_ENABLE;
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pm_io_write8(PM_LPC_GATING, byte);
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/* Enable port 80 LPC decode in pci function 3 configuration space. */
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byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
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byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */
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pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
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}
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void sb_lpc_decode(void)
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static void sb_lpc_decode(void)
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{
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u32 tmp = 0;
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@ -357,7 +226,11 @@ void sb_lpc_decode(void)
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| DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT
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| DECODE_ENABLE_ADLIB_PORT;
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pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp);
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/* Decode SIOs at 2E/2F and 4E/4F */
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if (CONFIG(STONEYRIDGE_LEGACY_FREE))
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tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
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lpc_enable_decode(tmp);
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}
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static void sb_enable_cf9_io(void)
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@ -397,43 +270,17 @@ void sb_clk_output_48Mhz(u32 osc)
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misc_write32(MISC_CLK_CNTL1, ctrl);
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}
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static uintptr_t sb_get_spibase(void)
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{
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u32 base;
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base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
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base = ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
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return (uintptr_t)base;
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}
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static void sb_set_spibase(u32 base, u32 enable)
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{
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u32 reg32;
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/* only two types of CS# enables are allowed */
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enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE;
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reg32 = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER);
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reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */
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reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE);
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reg32 |= enable;
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reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT);
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pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32);
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}
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static uintptr_t sb_init_spi_base(void)
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{
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uintptr_t base;
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/* Make sure the base address is predictable */
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base = sb_get_spibase();
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base = lpc_get_spibase();
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if (base)
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return base;
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sb_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
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lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE);
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return SPI_BASE_ADDRESS;
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}
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@ -464,109 +311,6 @@ void sb_read_mode(u32 mode)
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& ~SPI_READ_MODE_MASK) | mode);
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}
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/*
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* Enable FCH to decode TPM associated Memory and IO regions
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*
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* Enable decoding of TPM cycles defined in TPM 1.2 spec
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* Enable decoding of legacy TPM addresses: IO addresses 0x7f-
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* 0x7e and 0xef-0xee.
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* This function should be called if TPM is connected in any way to the FCH and
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* conforms to the regions decoded.
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* Absent any other routing configuration the TPM cycles will be claimed by the
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* LPC bus
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*/
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void sb_tpm_decode(void)
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{
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u32 value;
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value = pci_read_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE);
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value |= TPM_12_EN | TPM_LEGACY_EN;
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pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);
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}
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/*
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* Enable FCH to decode TPM associated Memory and IO regions to SPI
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*
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* This should be used if TPM is connected to SPI bus.
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* Assumes SPI address space is already configured.
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*/
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void sb_tpm_decode_spi(void)
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{
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/* Enable TPM decoding to FCH */
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sb_tpm_decode();
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/* Route TPM accesses to SPI */
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u32 spibase = pci_read_config32(SOC_LPC_DEV,
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SPIROM_BASE_ADDRESS_REGISTER);
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pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase
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| ROUTE_TPM_2_SPI);
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}
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/*
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* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
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*
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* Hardware should enable LPC ROM by pin straps. This function does not
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* handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
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*
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* The southbridge power-on default is to map 512K ROM space.
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*
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*/
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void sb_enable_rom(void)
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{
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u8 reg8;
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/*
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* Decode variable LPC ROM address ranges 1 and 2.
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* Bits 3-4 are not defined in any publicly available datasheet
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*/
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reg8 = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
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reg8 |= (1 << 3) | (1 << 4);
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pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8);
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/*
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* LPC ROM address range 1:
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* Enable LPC ROM range mirroring start at 0x000e(0000).
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*/
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pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e);
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/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
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pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f);
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/*
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* LPC ROM address range 2:
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*
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* Enable LPC ROM range start at:
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* 0xfff8(0000): 512KB
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* 0xfff0(0000): 1MB
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* 0xffe0(0000): 2MB
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* 0xffc0(0000): 4MB
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*/
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pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000
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- (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
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/* Enable LPC ROM range end at 0xffff(ffff). */
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pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff);
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}
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static void sb_lpc_early_setup(void)
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{
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uint32_t dword;
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/* Enable SPI prefetch */
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dword = pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL);
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dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN;
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pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword);
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if (CONFIG(STONEYRIDGE_LEGACY_FREE)) {
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/* Decode SIOs at 2E/2F and 4E/4F */
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dword = pci_read_config32(SOC_LPC_DEV,
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LPC_IO_OR_MEM_DECODE_ENABLE);
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dword |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE;
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pci_write_config32(SOC_LPC_DEV,
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LPC_IO_OR_MEM_DECODE_ENABLE, dword);
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}
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}
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static void setup_spread_spectrum(int *reboot)
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{
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uint16_t rstcfg = pm_read16(PWR_RESET_CFG);
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@ -649,10 +393,11 @@ void bootblock_fch_early_init(void)
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{
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int reboot = 0;
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sb_enable_rom();
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sb_lpc_port80();
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lpc_enable_rom();
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sb_enable_lpc();
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lpc_enable_port80();
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sb_lpc_decode();
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sb_lpc_early_setup();
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lpc_enable_spi_prefetch();
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sb_init_spi_base();
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sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */
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enable_acpimmio_decode();
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