intel/apollolake: Enable SPI properly in bootblock and ramstage

Bootblock:
   - Temporary BAR needs to be assigned for SPI device until PCI
   enumeration is done by ramstage which allocates a new BAR.
   - Call spi_init to allow bootblock/verstage to write/erase on flash.

Ramstage:
   - spi_init needs to run in ramstage to allow write protect to be
   disabled for eventlog and NVRAM updates. This needs to be done pretty
   early so that any init calls(e.g. mainboard_ec_init) writing to flash
   work properly.

Verified with this change that there are no more flash write/erase
errors for ELOG/NVRAM.

BUG=chrome-os-partner:54283

Change-Id: Iff840e055548485e6521889fcf264a10fb5d9491
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15209
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)

src/soc/intel/apollolake/chip.c

@@ -31,6 +31,7 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>
+#include <spi-generic.h>
 
 #include "chip.h"
 
@@ -164,3 +165,16 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy,
 						(void *) READY_TO_BOOT);
 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy,
 						(void *) READY_TO_BOOT);
+
+/*
+ * spi_init() needs to run unconditionally on every boot (including resume) to
+ * allow write protect to be disabled for eventlog and nvram updates. This needs
+ * to be done as early as possible in ramstage. Thus, add a callback for entry
+ * into BS_PRE_DEVICE.
+ */
+static void spi_init_cb(void *unused)
+{
+	spi_init();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL);