soc/intel/skylake: Add option to enable/disable EIST

Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.

Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/soc/intel/skylake/chip_fsp20.c

@@ -261,6 +261,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Enable PMC XRAM read */
 	tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
 
+	/* Enable/Disable EIST */
+	tconfig->Eist = config->eist_enable;
+
 	soc_irq_settings(params);
 }