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soc/intel/skylake: Add option to enable/disable EIST

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Set MSR 0x1A0 bit[16] based on EIST config option.
Default Hardware Managed P-state (HWP) also known as Intel Speed Shift
is enabled on SKL hence disable EIST and ACPI P-state table.

Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Subrata Banik
2017-05-12 11:43:57 +05:30
committed by Martin Roth
parent 481b364222
commit 6b45ee44a9
4 changed files with 19 additions and 4 deletions
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7
src/soc/intel/skylake/cpu.c
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@@ -245,12 +245,17 @@ static void configure_isst(void)
static void configure_misc(void)
{
device_t dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
if (conf->eist_enable)
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
else
msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */
wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */