soc/intel/alderlake: Switch to common eSPI header

This patch updates Alder Lake code to use the common eSPI header file
(`intelpch/espi.h`) instead of the SoC-specific one.

BUG=none
TEST=Builds successfully for google/redrix.

Change-Id: Ib4452547325042de48ee4fca3d3910a031b56b64
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83484
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/bootblock/pch.c

@@ -16,9 +16,9 @@
 #include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
+#include <intelpch/espi.h>
 #include <soc/bootblock.h>
 #include <soc/soc_chip.h>
-#include <soc/espi.h>
 #include <soc/iomap.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>

src/soc/intel/alderlake/espi.c

@@ -13,7 +13,7 @@
 #include <intelblocks/itss.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
-#include <soc/espi.h>
+#include <intelpch/espi.h>
 #include <soc/iomap.h>
 #include <soc/irq.h>
 #include <soc/pci_devs.h>

src/soc/intel/alderlake/include/soc/espi.h

@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 2
- */
-
-#ifndef _SOC_ALDERLAKE_ESPI_H_
-#define _SOC_ALDERLAKE_ESPI_H_
-
-/* PCI Configuration Space (D31:F0): ESPI */
-#define SCI_IRQ_SEL		(7 << 0)
-#define SCIS_IRQ9		0
-#define SCIS_IRQ10		1
-#define SCIS_IRQ11		2
-#define SCIS_IRQ20		4
-#define SCIS_IRQ21		5
-#define SCIS_IRQ22		6
-#define SCIS_IRQ23		7
-#define SERIRQ_CNTL		0x64
-#define ESPI_IO_DEC		0x80 /* IO Decode Ranges Register */
-#define   COMA_RANGE		0x0 /* 0x3F8 - 0x3FF COM1*/
-#define   COMB_RANGE		0x1 /* 0x2F8 - 0x2FF COM2*/
-#define ESPI_GEN1_DEC		0x84 /* ESPI IF Generic Decode Range 1 */
-#define ESPI_GEN2_DEC		0x88 /* ESPI IF Generic Decode Range 2 */
-#define ESPI_GEN3_DEC		0x8c /* ESPI IF Generic Decode Range 3 */
-#define ESPI_GEN4_DEC		0x90 /* ESPI IF Generic Decode Range 4 */
-#define LGMR			0x98 /* ESPI Generic Memory Range */
-#define PCCTL			0xE0 /* PCI Clock Control */
-#define   CLKRUN_EN		(1 << 0)
-
-#endif

src/soc/intel/alderlake/pmutil.c

@@ -22,8 +22,8 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
+#include <intelpch/espi.h>
 #include <security/vboot/vbnv.h>
-#include <soc/espi.h>
 #include <soc/gpe.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>