sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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committed by
Patrick Georgi
parent
4821a0e135
commit
6beaef983a
@@ -28,7 +28,7 @@ func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File,
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}
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for i := uint(0); i < max; i++ {
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if ((constraint>>i)&1 == 1) {
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if (constraint>>i)&1 == 1 {
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fmt.Fprintf(sb, " .gpio%d = %s,\n",
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(set-1)*32+i,
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bits[partno][(val>>i)&1])
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@@ -236,8 +236,8 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
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"p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)),
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"c2_latency": FormatHexLE16(FADT[96:98]),
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"docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)),
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"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
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"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4] &^ (1 << 23)),
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"spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]),
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"spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)),
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},
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"},
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@@ -315,10 +315,6 @@ void pch_enable_lpc(void)
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{
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`)
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RestorePCI16Simple(sb, addr, 0x82)
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RestorePCI32Simple(sb, addr, 0x84)
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RestorePCI32Simple(sb, addr, 0x88)
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RestorePCI32Simple(sb, addr, 0x8c)
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RestorePCI32Simple(sb, addr, 0x90)
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RestorePCI16Simple(sb, addr, 0x80)
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