soc/qualcomm/qcs405: Add MMU support

Initialize 1st 4GB as Device Memory, except:
 * 1st page: NULL address
 * System_IMEM: Cached SRAM
 * Boot_IMEM: Cached SRAM

Change-Id: I8c6353be2c0379ec94f91223805762a2286de06d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/soc/qualcomm/qcs405/Makefile.inc

@@ -5,6 +5,7 @@ ifeq ($(CONFIG_SOC_QUALCOMM_QCS405),y)
 bootblock-y += bootblock.c
 bootblock-y += timer.c
 bootblock-y += spi.c
+bootblock-y += mmu.c
 
 ################################################################################
 verstage-y += timer.c

src/soc/qualcomm/qcs405/bootblock.c

@@ -14,8 +14,9 @@
  */
 
 #include <bootblock_common.h>
+#include <soc/mmu.h>
 
 void bootblock_soc_init(void)
 {
-
+	qcs405_mmu_init();
 }

src/soc/qualcomm/qcs405/include/soc/mmu.h

@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_QCS405_MMU_H__
+#define _SOC_QUALCOMM_QCS405_MMU_H__
+
+void qcs405_mmu_init(void);
+
+#endif  // _SOC_QUALCOMM_QCS405_MMU_H_

src/soc/qualcomm/qcs405/include/soc/symbols.h

@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_QCS405_SYMBOLS_H_
+#define _SOC_QUALCOMM_QCS405_SYMBOLS_H_
+
+#include <symbols.h>
+#include <types.h>
+
+DECLARE_REGION(ssram);
+DECLARE_REGION(bsram);
+
+#endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_

src/soc/qualcomm/qcs405/mmu.c

@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <symbols.h>
+#include <arch/mmu.h>
+#include <arch/cache.h>
+#include <soc/mmu.h>
+#include <soc/symbols.h>
+
+void qcs405_mmu_init(void)
+{
+	mmu_init();
+
+	mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)),
+			MA_DEV | MA_S | MA_RW);
+	mmu_config_range((void *)_ssram, REGION_SIZE(ssram), MA_MEM | MA_S | MA_RW);
+	mmu_config_range((void *)_bsram, REGION_SIZE(bsram), MA_MEM | MA_S | MA_RW);
+
+	mmu_enable();
+}