stoneyridge: Fix CPU ASL \_PR table

The PMIO region was moved, but not updated in the ASL. Change to
generate \_PR table runtime and to report the correct PMIO region
and length.

Fix on Kahlee, where the EC overlaps the region:
[    0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0
[    0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16

BUG=b:63902389
BRANCH=none
TEST=Cros_ec_lps can reserve the region. ACPI tables are correct.

Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/stoneyridge/chip.c

@@ -32,6 +32,7 @@ struct device_operations cpu_bus_ops = {
 	.enable_resources = DEVICE_NOOP,
 	.init		  = &cpu_bus_init,
 	.scan_bus	  = cpu_bus_scan,
+	.acpi_fill_ssdt_generator = generate_cpu_entries,
 };
 
 struct device_operations pci_domain_ops = {