soc/amd/common/data_fabric: pass PCI segment group to domain code

Return the PCI segment group number from data_fabric_get_pci_bus_numbers
via pointer argument so that amd_pci_domain_scan_bus can handle the PCI
segment group numbers once coreboot supports more than one PCI segment
group. For now, just print an error and return if the buses are on a PCI
segment group other than 0.

TEST=Mandolin still boots

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia53cda0ba656201c2197d05bc0d4a8fbbe8ad5d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

src/soc/amd/common/block/data_fabric/domain.c

@@ -14,13 +14,19 @@
 
 void amd_pci_domain_scan_bus(struct device *domain)
 {
-	uint8_t bus, limit;
+	uint8_t segment_group, bus, limit;
 
-	if (data_fabric_get_pci_bus_numbers(domain, &bus, &limit) != CB_SUCCESS) {
+	if (data_fabric_get_pci_bus_numbers(domain, &segment_group, &bus, &limit) != CB_SUCCESS) {
 		printk(BIOS_ERR, "No PCI bus numbers decoded to PCI root.\n");
 		return;
 	}
 
+	/* TODO: Implement support for more than one PCI segment group in coreboot */
+	if (segment_group) {
+		printk(BIOS_ERR, "coreboot currently only supports one PCI segment group.\n");
+		return;
+	}
+
 	/* TODO: Check if bus >= CONFIG_ECAM_MMCONF_BUS_NUMBER and return in that case */
 
 	/* Make sure to not report more than CONFIG_ECAM_MMCONF_BUS_NUMBER PCI buses */

src/soc/amd/common/block/data_fabric/pci_segment_multi.c

@@ -6,8 +6,8 @@
 #include <device/device.h>
 #include <types.h>
 
-enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *first_bus,
+enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *segment_group,
-					    uint8_t *last_bus)
+					    uint8_t *first_bus, uint8_t *last_bus)
 {
 	const signed int iohc_dest_fabric_id = get_iohc_fabric_id(domain);
 	union df_pci_cfg_base pci_bus_base;
@@ -21,13 +21,7 @@ enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *firs
 			continue;
 
 		if (pci_bus_base.we && pci_bus_base.re) {
-			/* TODO: Implement support for multiple PCI segments in coreboot */
+			*segment_group = pci_bus_base.segment_num;
-			if (pci_bus_base.segment_num) {
-				printk(BIOS_ERR, "DF PCI CFG register pair %d uses bus "
-						 "segment != 0.\n", i);
-				return CB_ERR;
-			}
-
 			*first_bus = pci_bus_base.bus_num_base;
 			*last_bus = pci_bus_limit.bus_num_limit;
 			return CB_SUCCESS;

src/soc/amd/common/block/data_fabric/pci_segment_single.c

@@ -6,8 +6,8 @@
 #include <device/device.h>
 #include <types.h>
 
-enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *first_bus,
+enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *segment_group,
-					    uint8_t *last_bus)
+					    uint8_t *first_bus, uint8_t *last_bus)
 {
 	const signed int iohc_dest_fabric_id = get_iohc_fabric_id(domain);
 	union df_pci_cfg_map pci_bus_map;
@@ -19,6 +19,7 @@ enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *firs
 			continue;
 
 		if (pci_bus_map.we && pci_bus_map.re) {
+			*segment_group = 0;
 			*first_bus = pci_bus_map.bus_num_base;
 			*last_bus = pci_bus_map.bus_num_limit;
 			return CB_SUCCESS;

src/soc/amd/common/block/include/amdblocks/data_fabric.h

@@ -49,8 +49,8 @@ void data_fabric_broadcast_write32(uint16_t fn_reg, uint32_t data)
 void data_fabric_print_mmio_conf(void);
 void data_fabric_set_mmio_np(void);
 
-enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *first_bus,
+enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *segment_group,
-					    uint8_t *last_bus);
+					    uint8_t *first_bus, uint8_t *last_bus);
 
 void data_fabric_get_mmio_base_size(unsigned int reg, resource_t *mmio_base,
 				    resource_t *mmio_limit);