drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config

Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash.  If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y.  This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.

BUG=b:150502246
BRANCH=None

TEST=diff the coreboot.rom files resulting from running
     ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
     with and without this change to make sure that there was no
     difference.  Also did this for GOOGLE_CANDY board, which is
     baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
     enabled).

Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/cpu/intel/haswell/Kconfig

@@ -7,6 +7,7 @@ if CPU_INTEL_HASWELL
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_ALL_STAGES_X86_32
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select MMX
 	select SSE2
 	select UDELAY_TSC

src/cpu/intel/model_2065x/Kconfig

@@ -6,6 +6,7 @@ if CPU_INTEL_MODEL_2065X
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_ALL_STAGES_X86_32
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select SSE2
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER

src/cpu/intel/model_206ax/Kconfig

@@ -6,6 +6,7 @@ if CPU_INTEL_MODEL_206AX
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_ALL_STAGES_X86_32
+	select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
 	select MMX
 	select SSE2
 	select UDELAY_TSC