Documentation: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Documentation/mainboard/amd/padmelon/padmelon.md

@@ -43,7 +43,7 @@ Three items are marked in this picture
 +---------------------+--------------------+
 | Size                | 8 MiB              |
 +---------------------+--------------------+
-| Flash programing    | dediprog header    |
+| Flash programming   | dediprog header    |
 +---------------------+--------------------+
 | Package             | SOIC-8             |
 +---------------------+--------------------+

Documentation/mainboard/emulation/qemu-aarch64.md

@@ -1,5 +1,5 @@
 # QEMU AArch64 emulator
-This page discribes how to build and run coreboot for QEMU/AArch64.
+This page describes how to build and run coreboot for QEMU/AArch64.
 You can use LinuxBoot via `make menuconfig` or an arbitrary FIT image
 as a payload for QEMU/AArch64.
 

Documentation/mainboard/lenovo/Ivy_Bridge_series.md

@@ -76,7 +76,7 @@ region. The update is then written into the EC once.
 
 [fl]: flashlayout_Ivy_Bridge.svg
 
-## Reducing Intel Managment Engine firmware size
+## Reducing Intel Management Engine firmware size
 
 It is possible to reduce the Intel ME firmware size to free additional
 space for the `bios` region. This is usually referred to as *cleaning the ME* or

Documentation/mainboard/lenovo/Sandy_Bridge_series.md

@@ -48,7 +48,7 @@ region. The update is then written into the EC once.
 
 [fl]: flashlayout_Sandy_Bridge.svg
 
-## Reducing Intel Managment Engine firmware size
+## Reducing Intel Management Engine firmware size
 
 It is possible to reduce the Intel ME firmware size to free additional
 space for the `bios` region. This is usually referred to as *cleaning the ME* or

Documentation/mainboard/lenovo/vboot.md

@@ -28,7 +28,7 @@ to boot and flash a working image to the A/B partition.
 
 ## 8 MiB ROM limitation
 *Lenovo* devices with 8 MiB ROM only have a `RO`+`A` partition enabled in the
-default FMAP. They are missing the `B` partition, due to size constaints.
+default FMAP. They are missing the `B` partition, due to size constraints.
 You can still provide your own FMAP if you need `RO`+`A`+`B` partitions.
 
 ## CMOS

Documentation/mainboard/ocp/tiogapass.md

@@ -51,7 +51,7 @@ To connect to console through SOL (Serial Over Lan):
 
 ## Known issues / feature gaps
 - C6 state is not supported. Workaround is to disable C6 support through
-  target OS and Linuxboot kernel paramter, such as "cpuidle.off=1".
+  target OS and Linuxboot kernel parameter, such as "cpuidle.off=1".
 - SMI handlers are not implemented.
 - xSDT tables are not fully populated, such as processor/socket devices,
   PCIe bridge devices.

Documentation/mainboard/up/squared/index.md

@@ -48,7 +48,7 @@
 +---------------------+------------+
 | Internal flashing   | No         |
 +---------------------+------------+
-| In curcuit flashing | Yes        |
+| In circuit flashing | Yes        |
 +---------------------+------------+
 ```
 
@@ -67,8 +67,8 @@ The GPIO header is located on the **bottom** side (see [here][overview_bottom_li
 The SPI header is located on the **bottom** side (see [here][overview_bottom_link]).
 ![][header_cn22]
 
-### Preperations
-In order to build coreboot, it's neccessary to extract some files from the vendor firmware. Make sure that you have a fully working dump.
+### Preparations
+In order to build coreboot, it's necessary to extract some files from the vendor firmware. Make sure that you have a fully working dump.
 ```bash
 [upsquared]$ ls
 firmware_vendor.rom