Documentation: Fix spelling errors

These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

Documentation/northbridge/intel/sandybridge/nri.md

@@ -40,7 +40,7 @@ The memory initialization code has to take care of lots of duties:
 +---------+-------------------------------------------------------------------+------------+--------------+
 ```
 
-## (Unoffical) register documentation
+## (Unofficial) register documentation
 - [Sandy Bridge - Register documentation](nri_registers.md)
 
 ## Frequency selection
@@ -101,7 +101,7 @@ is stored to MRC cache.
 As of writing the only supported error handling is to disable the failing
 channel and restart the memory training sequence. It's very likely to succeed,
 as memory channels operate independent of each other.
-In case no DIMM could be initilized coreboot will halt. The screen will stay
+In case no DIMM could be initialized coreboot will halt. The screen will stay
 black until you power of your device. On some platforms there's additional
 feedback to indicate such an event.
 

Documentation/northbridge/intel/sandybridge/nri_freq.md

@@ -42,7 +42,7 @@ Only **XMP profile 1** is being used in case it advertises:
 * 1.5V operating voltage
 * The channel's installed DIMM count doesn't exceed the XMP coded limit
 
-In case the XMP profile doesn't fullfill those limits, the regular SPD will be
+In case the XMP profile doesn't fulfill those limits, the regular SPD will be
 used.
 > **Note:** XMP Profiles are supported since coreboot 4.4.
 

Documentation/northbridge/intel/sandybridge/nri_registers.md

@@ -1947,7 +1947,7 @@ Please handle with care!
 +-----------+------------------------------------------------------------------+
 | Bit       | Description                                                      |
 +===========+==================================================================+
-|        0:7|  OREF_RI, Rank idle period that defines an oppertunity for       |
+|        0:7|  OREF_RI, Rank idle period that defines an opportunity for       |
 |           |  refresh                                                         |
 +-----------+------------------------------------------------------------------+
 |       8:11|  Refresh_HP_WM, tREFI count level that turns the refresh         |