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soc/intel/xeon_sp: Add domain resource window creation utils

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It might be benefical to have utils for domain resource window
creation so that the correct IORESOURCE flags used could be
guaranteed.

TEST=Build and boot on intel/archercity CRB
TEST=Build on intel/avenuecity CRB

Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Shuo Liu
2024-04-29 18:16:30 +08:00
committed by Lean Sheng Tan
parent 94bfdd1282
commit 6c708d8a46
5 changed files with 81 additions and 85 deletions
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9
src/device/device_util.c
View File

@@ -776,7 +776,7 @@ void show_all_devs_resources(int debug_level, const char *msg)
}
}
const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index,
const struct resource *resource_range_idx(struct device *dev, unsigned long index,
uint64_t base, uint64_t size, unsigned long flags)
{
struct resource *resource;
@@ -785,8 +785,13 @@ const struct resource *fixed_resource_range_idx(struct device *dev, unsigned lon
resource = new_resource(dev, index);
resource->base = base;
if (flags & IORESOURCE_FIXED)
resource->size = size;
resource->flags = IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
if (flags & IORESOURCE_BRIDGE)
resource->limit = base + size - 1;
resource->flags = IORESOURCE_ASSIGNED;
resource->flags |= flags;
printk(BIOS_SPEW, "dev: %s, index: 0x%lx, base: 0x%llx, size: 0x%llx\n",

43
src/include/device/device.h
View File

@@ -263,7 +263,7 @@ void mmconf_resource(struct device *dev, unsigned long index);
/* These are temporary resource constructors to get us through the
migration away from open-coding all the IORESOURCE_FLAGS. */
const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index,
const struct resource *resource_range_idx(struct device *dev, unsigned long index,
uint64_t base, uint64_t size,
unsigned long flags);
@@ -272,7 +272,8 @@ const struct resource *fixed_mem_range_flags(struct device *dev, unsigned long i
uint64_t base, uint64_t size,
unsigned long flags)
{
return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_MEM | flags);
return resource_range_idx(dev, index, base, size,
IORESOURCE_FIXED | IORESOURCE_MEM | flags);
}
static inline
@@ -284,6 +285,24 @@ const struct resource *fixed_mem_from_to_flags(struct device *dev, unsigned long
return fixed_mem_range_flags(dev, index, base, end - base, flags);
}
static inline
const struct resource *domain_mem_window_range(struct device *dev, unsigned long index,
uint64_t base, uint64_t size)
{
return resource_range_idx(dev, index, base, size,
IORESOURCE_MEM | IORESOURCE_BRIDGE);
}
static inline
const struct resource *domain_mem_window_from_to(struct device *dev, unsigned long index,
uint64_t base, uint64_t end)
{
if (end <= base)
return NULL;
return domain_mem_window_range(dev, index, base, end - base);
}
static inline
const struct resource *ram_range(struct device *dev, unsigned long index, uint64_t base,
uint64_t size)
@@ -344,7 +363,8 @@ static inline
const struct resource *fixed_io_range_flags(struct device *dev, unsigned long index,
uint16_t base, uint16_t size, unsigned long flags)
{
return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_IO | flags);
return resource_range_idx(dev, index, base, size,
IORESOURCE_FIXED | IORESOURCE_IO | flags);
}
static inline
@@ -363,6 +383,23 @@ const struct resource *fixed_io_range_reserved(struct device *dev, unsigned long
return fixed_io_range_flags(dev, index, base, size, IORESOURCE_RESERVE);
}
static inline
const struct resource *domain_io_window_range(struct device *dev, unsigned long index,
uint16_t base, uint16_t size)
{
return resource_range_idx(dev, index, base, size,
IORESOURCE_IO | IORESOURCE_BRIDGE);
}
static inline
const struct resource *domain_io_window_from_to(struct device *dev, unsigned long index,
uint16_t base, uint16_t end)
{
if (end <= base)
return NULL;
return domain_io_window_range(dev, index, base, end - base);
}
/* Compatibility code */
static inline void fixed_mem_resource_kb(struct device *dev, unsigned long index,

64
src/soc/intel/xeon_sp/chip_gen1.c
View File

@@ -27,7 +27,6 @@ static const STACK_RES *domain_to_stack_res(const struct device *dev)
static void iio_pci_domain_read_resources(struct device *dev)
{
struct resource *res;
const STACK_RES *sr = domain_to_stack_res(dev);
if (!sr)
@@ -37,36 +36,24 @@ static void iio_pci_domain_read_resources(struct device *dev)
if (is_domain0(dev)) {
/* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */
res = new_resource(dev, index++);
struct resource *res = new_resource(dev, index++);
res->base = 0;
res->size = 0x1000;
res->limit = 0xfff;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
if (sr->PciResourceIoBase < sr->PciResourceIoLimit) {
res = new_resource(dev, index++);
res->base = sr->PciResourceIoBase;
res->limit = sr->PciResourceIoLimit;
res->size = res->limit - res->base + 1;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
}
if (sr->PciResourceIoBase < sr->PciResourceIoLimit)
domain_io_window_from_to(dev, index++,
sr->PciResourceIoBase, sr->PciResourceIoLimit + 1);
if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit) {
res = new_resource(dev, index++);
res->base = sr->PciResourceMem32Base;
res->limit = sr->PciResourceMem32Limit;
res->size = res->limit - res->base + 1;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
}
if (sr->PciResourceMem32Base < sr->PciResourceMem32Limit)
domain_mem_window_from_to(dev, index++,
sr->PciResourceMem32Base, sr->PciResourceMem32Limit + 1);
if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) {
res = new_resource(dev, index++);
res->base = sr->PciResourceMem64Base;
res->limit = sr->PciResourceMem64Limit;
res->size = res->limit - res->base + 1;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
}
if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit)
domain_mem_window_from_to(dev, index++,
sr->PciResourceMem64Base, sr->PciResourceMem64Limit + 1);
}
/*
@@ -129,7 +116,6 @@ void create_cxl_domains(const union xeon_domain_path dp, struct bus *bus,
#if CONFIG(SOC_INTEL_HAS_CXL)
static void iio_cxl_domain_read_resources(struct device *dev)
{
struct resource *res;
const STACK_RES *sr = domain_to_stack_res(dev);
if (!sr)
@@ -137,29 +123,17 @@ static void iio_cxl_domain_read_resources(struct device *dev)
int index = 0;
if (sr->IoBase < sr->PciResourceIoBase) {
res = new_resource(dev, index++);
res->base = sr->IoBase;
res->limit = sr->PciResourceIoBase - 1;
res->size = res->limit - res->base + 1;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
}
if (sr->IoBase < sr->PciResourceIoBase)
domain_io_window_from_to(dev, index++,
sr->IoBase, sr->PciResourceIoBase);
if (sr->Mmio32Base < sr->PciResourceMem32Base) {
res = new_resource(dev, index++);
res->base = sr->Mmio32Base;
res->limit = sr->PciResourceMem32Base - 1;
res->size = res->limit - res->base + 1;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
}
if (sr->Mmio32Base < sr->PciResourceMem32Base)
domain_mem_window_from_to(dev, index++,
sr->Mmio32Base, sr->PciResourceMem32Base);
if (sr->Mmio64Base < sr->PciResourceMem64Base) {
res = new_resource(dev, index++);
res->base = sr->Mmio64Base;
res->limit = sr->PciResourceMem64Base - 1;
res->size = res->limit - res->base + 1;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
}
if (sr->Mmio64Base < sr->PciResourceMem64Base)
domain_mem_window_from_to(dev, index++,
sr->Mmio64Base, sr->PciResourceMem64Base);
}
static struct device_operations iio_cxl_domain_ops = {

30
src/soc/intel/xeon_sp/chip_gen6.c
View File

@@ -35,20 +35,16 @@ static const UDS_PCIROOT_RES *domain_to_pciroot_res(const struct device *dev)
static void iio_pci_domain_read_resources(struct device *dev)
{
int index = 0;
struct resource *res;
const UDS_PCIROOT_RES *pr = domain_to_pciroot_res(dev);
/* Initialize the system-wide I/O space constraints. */
if (pr->IoBase <= pr->IoLimit) {
res = new_resource(dev, index++);
res->base = pr->IoBase;
res->limit = pr->IoLimit;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED;
}
if (pr->IoBase <= pr->IoLimit)
domain_io_window_from_to(dev, index++,
pr->IoBase, pr->IoLimit + 1);
/* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */
if (is_domain0(dev)) {
res = new_resource(dev, index++);
struct resource *res = new_resource(dev, index++);
res->base = 0;
res->limit = 0xfff;
res->size = 0x1000;
@@ -56,20 +52,14 @@ static void iio_pci_domain_read_resources(struct device *dev)
}
/* Initialize the system-wide memory resources constraints. */
if (pr->Mmio32Base <= pr->Mmio32Limit) {
res = new_resource(dev, index++);
res->base = pr->Mmio32Base;
res->limit = pr->Mmio32Limit;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
}
if (pr->Mmio32Base <= pr->Mmio32Limit)
domain_mem_window_from_to(dev, index++,
pr->Mmio32Base, pr->Mmio32Limit + 1);
/* Initialize the system-wide memory resources constraints. */
if (pr->Mmio64Base <= pr->Mmio64Limit) {
res = new_resource(dev, index++);
res->base = pr->Mmio64Base;
res->limit = pr->Mmio64Limit;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
}
if (pr->Mmio64Base <= pr->Mmio64Limit)
domain_mem_window_from_to(dev, index++,
pr->Mmio64Base, pr->Mmio64Limit + 1);
}
static struct device_operations iio_pcie_domain_ops = {

18
src/soc/intel/xeon_sp/spr/ioat.c
View File

@@ -61,21 +61,11 @@ static void create_ioat_domain(const union xeon_domain_path dp, struct bus *cons
unsigned int index = 0;
if (mem32_base <= mem32_limit) {
struct resource *const res = new_resource(domain, index++);
res->base = mem32_base;
res->limit = mem32_limit;
res->size = res->limit - res->base + 1;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
}
if (mem32_base <= mem32_limit)
domain_mem_window_from_to(domain, index++, mem32_base, mem32_limit + 1);
if (mem64_base <= mem64_limit) {
struct resource *const res = new_resource(domain, index++);
res->base = mem64_base;
res->limit = mem64_limit;
res->size = res->limit - res->base + 1;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED;
}
if (mem64_base <= mem64_limit)
domain_mem_window_from_to(domain, index++, mem64_base, mem64_limit + 1);
}
void create_ioat_domains(const union xeon_domain_path path,