Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical)
220
src/cpu/amd/car/cache_as_ram.inc
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220
src/cpu/amd/car/cache_as_ram.inc
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@@ -0,0 +1,220 @@
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/* by yhlu 6.2005 */
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/* We will use 4K bytes only */
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#define CacheSize DCACHE_RAM_SIZE
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#define CacheBase (0xd0000 - CacheSize)
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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/* Save the BIST result */
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movl %eax, %ebp
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CacheAsRam:
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/* hope we can skip the double set for normal part */
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#if USE_FALLBACK_IMAGE == 1
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/* Set MtrrFixDramModEn for clear fixed mtrr */
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xorl %eax, %eax # clear %eax and %edx
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xorl %edx, %edx
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enable_fixed_mtrr_dram_modify:
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movl $SYSCFG_MSR, %ecx
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rdmsr
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andl $(~(SYSCFG_MSR_MtrrFixDramEn|SYSCFG_MSR_MtrrVarDramEn)), %eax
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orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
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wrmsr
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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wrmsr
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/*Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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/* Enable the MTRRs and IORRs in SYSCFG */
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movl $SYSCFG_MSR, %ecx
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rdmsr
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orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
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wrmsr
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#if 1
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#if CacheSize == 0x10000
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/* enable caching for 64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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movl $0x269, %ecx
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wrmsr
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#endif
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#if CacheSize == 0x8000
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/* enable caching for 32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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movl $0x06060606, %eax /* WB IO type */
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movl %eax, %edx
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wrmsr
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#endif
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/* enable caching for 16K/8K/4K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_cc000*/
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#if CacheSize == 0x4000
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movl $0x06060606, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x2000
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movl $0x06060000, %edx /* WB IO type */
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#endif
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#if CacheSize == 0x1000
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movl $0x06000000, %edx /* WB IO type */
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#endif
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xorl %eax, %eax
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wrmsr
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#else
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/* enable caching for 64K using variable mtrr */
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movl $0x200, %ecx
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xorl %edx, %edx
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movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
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wrmsr
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movl $0x201, %ecx
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movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
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movl $((~((CacheBase + CacheSize) - 1)) | 0x800), %eax
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wrmsr
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/* make it to be IO by clearing RD Dram and WR Dram */
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movl $IORR0_BASE, %ecx
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xorl %edx, %edx
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movl $CacheBase, %eax /* bit 3, and bit 4 = 0 mean clear RD ram and WR ram */
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wrmsr
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movl $IORR0_MASK, %ecx
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movl $0x000000ff, %edx
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movl $(~((CacheBase + CacheSize) - 1) | 0x800), %eax
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wrmsr
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#endif
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/* enable memory access for 0 - 1MB using top_mem */
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movl $TOP_MEM, %ecx
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xorl %edx, %edx
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movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
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wrmsr
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#else
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/* disable cache */
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movl %cr0, %eax
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orl $(0x1<<30),%eax
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movl %eax, %cr0
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#endif /* USE_FALLBACK_IMAGE == 1*/
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#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
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/* enable write base caching so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
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wrmsr
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movl $0x203, %ecx
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movl $0x0000000f, %edx
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movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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#if USE_FALLBACK_IMAGE == 1
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/* Read the range with lodsl*/
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movl $(CacheBase+CacheSize-4), %esi
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std
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movl $(CacheSize>>2), %ecx
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rep lodsl
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/* Clear the range */
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movl $(CacheBase+CacheSize-4), %edi
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movl $(CacheSize>>2), %ecx
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xorl %eax, %eax
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rep stosl
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#if 0
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/* check the cache as ram */
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movl $CacheBase, %esi
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movl $(CacheSize>>2), %ecx
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.xin1:
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movl %esi, %eax
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movl %eax, (%esi)
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movl $0x1000, %edx
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movb %ah, %al
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.testx1:
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outb %al, $0x80
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decl %edx
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jnz .testx1
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movl (%esi), %eax
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cmpb 0xff, %al
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je .xin2 /* dont show */
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movl $0x1000, %edx
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.testx2:
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outb %al, $0x80
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decl %edx
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jnz .testx2
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.xin2: decl %ecx
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je .xout1
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add $4, %esi
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jmp .xin1
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.xout1:
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#endif
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#endif /*USE_FALLBACK_IMAGE == 1*/
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movl $(CacheBase+CacheSize-4), %eax
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movl %eax, %esp
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/* Restore the BIST result */
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movl %ebp, %eax
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/* We need to set ebp ? No need */
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movl %esp, %ebp
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pushl %eax /* bist */
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call amd64_main
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/* We will not go back */
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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var_iorr_msr:
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.long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
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mem_top:
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.long 0xC001001A, 0xC001001D
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.long 0x000 /* NULL, end of table */
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.CacheAsRam_out:
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17
src/cpu/amd/car/cache_as_ram.lds
Normal file
17
src/cpu/amd/car/cache_as_ram.lds
Normal file
@@ -0,0 +1,17 @@
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/*
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* init sections to place code running with cache as ram.
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*
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* 2004 by Stefan Reinauer <stepan@openbios.org>
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*/
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SECTIONS {
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.init . : {
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_init = .;
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*(.init.text);
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*(.init.rodata);
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*(.init.rodata.*);
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. = ALIGN(16);
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_einit = .;
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}
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}
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94
src/cpu/amd/car/cache_as_ram_post.c
Normal file
94
src/cpu/amd/car/cache_as_ram_post.c
Normal file
@@ -0,0 +1,94 @@
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/* by yhlu 6.2005 */
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__asm__ volatile (
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/*
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FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
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It is only needed if we want to go back
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*/
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/* We don't need cache as ram for now on */
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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/* clear sth */
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"movl $0x269, %ecx\n\t" /* fix4k_c8000*/
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"xorl %edx, %edx\n\t"
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"xorl %eax, %eax\n\t"
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"wrmsr\n\t"
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#if DCACHE_RAM_SIZE > 0x8000
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"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
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"wrmsr\n\t"
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#endif
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/* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
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"movl $0xC0010010, %ecx\n\t"
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// "movl $SYSCFG_MSR, %ecx\n\t"
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"rdmsr\n\t"
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"andl $(~(3<<18)), %eax\n\t"
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// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
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"wrmsr\n\t"
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/* Set the default memory type and disable fixed and enable variable MTRRs */
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"movl $0x2ff, %ecx\n\t"
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// "movl $MTRRdefType_MSR, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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/* Enable Variable and Disable Fixed MTRRs */
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"movl $0x00000800, %eax\n\t"
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"wrmsr\n\t"
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#if defined(CLEAR_FIRST_1M_RAM)
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/* enable caching for first 1M using variable mtrr */
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"movl $0x200, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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"movl $(0 | 1), %eax\n\t"
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// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
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"wrmsr\n\t"
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"movl $0x201, %ecx\n\t"
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"movl $0x0000000f, %edx\n\t"
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"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
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"wrmsr\n\t"
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#endif
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/* enable cache */
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"movl %cr0, %eax\n\t"
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"andl $0x9fffffff,%eax\n\t"
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"movl %eax, %cr0\n\t"
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#if defined(CLEAR_FIRST_1M_RAM)
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/* clear the first 1M */
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"movl $0x0, %edi\n\t"
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"cld\n\t"
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"movl $(0x100000>>2), %ecx\n\t"
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"xorl %eax, %eax\n\t"
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"rep stosl\n\t"
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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/* enable caching for first 1M using variable mtrr */
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"movl $0x200, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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"movl $(0 | 6), %eax\n\t"
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// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
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"wrmsr\n\t"
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"movl $0x201, %ecx\n\t"
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"movl $0x0000000f, %edx\n\t"
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"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
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"wrmsr\n\t"
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/* enable cache */
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"movl %cr0, %eax\n\t"
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"andl $0x9fffffff,%eax\n\t"
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"movl %eax, %cr0\n\t"
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"invd\n\t"
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/*
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FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back
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But the problem is the range is some io related, So don't go back
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*/
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#endif
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);
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132
src/cpu/amd/car/copy_and_run.c
Normal file
132
src/cpu/amd/car/copy_and_run.c
Normal file
@@ -0,0 +1,132 @@
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/* by yhlu 6.2005
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moved from nrv2v.c and some lines from crt0.S
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*/
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#ifndef ENDIAN
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#define ENDIAN 0
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#endif
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#ifndef BITSIZE
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#define BITSIZE 32
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#endif
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#define GETBIT_8(bb, src, ilen) \
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(((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1)
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#define GETBIT_LE16(bb, src, ilen) \
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(bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1))
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#define GETBIT_LE32(bb, src, ilen) \
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(bc > 0 ? ((bb>>--bc)&1) : (bc=31,\
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bb=*(const uint32_t *)((src)+ilen),ilen+=4,(bb>>31)&1))
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#if ENDIAN == 0 && BITSIZE == 8
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#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen)
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#endif
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#if ENDIAN == 0 && BITSIZE == 16
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#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen)
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#endif
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#if ENDIAN == 0 && BITSIZE == 32
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#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
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#endif
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static void copy_and_run(unsigned cpu_reset)
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{
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uint8_t *src, *dst;
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unsigned long dst_len;
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unsigned long ilen = 0, olen = 0, last_m_off = 1;
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uint32_t bb = 0;
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unsigned bc = 0;
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print_debug("Copying LinuxBIOS to ram.\r\n");
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#if !CONFIG_COMPRESS
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__asm__ volatile (
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"leal _liseg, %0\n\t"
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"leal _iseg, %1\n\t"
|
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"leal _eiseg, %2\n\t"
|
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"subl %1, %2\n\t"
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: "=a" (src), "=b" (dst), "=c" (dst_len)
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);
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memcpy(src, dst, dst_len);
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#else
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__asm__ volatile (
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"leal 4+_liseg, %0\n\t"
|
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"leal _iseg, %1\n\t"
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: "=a" (src) , "=b" (dst)
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);
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#if CONFIG_USE_INIT
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printk_debug("src=%08x\r\n",src);
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printk_debug("dst=%08x\r\n",dst);
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#else
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print_debug("src="); print_debug_hex32(src); print_debug("\r\n");
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print_debug("dst="); print_debug_hex32(dst); print_debug("\r\n");
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#endif
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for(;;) {
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unsigned int m_off, m_len;
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while(GETBIT(bb, src, ilen)) {
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dst[olen++] = src[ilen++];
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}
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m_off = 1;
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do {
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m_off = m_off*2 + GETBIT(bb, src, ilen);
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} while (!GETBIT(bb, src, ilen));
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if (m_off == 2)
|
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{
|
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m_off = last_m_off;
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}
|
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else
|
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{
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m_off = (m_off - 3)*256 + src[ilen++];
|
||||
if(m_off == 0xffffffffU)
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break;
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last_m_off = ++m_off;
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}
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m_len = GETBIT(bb, src, ilen);
|
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m_len = m_len*2 + GETBIT(bb, src, ilen);
|
||||
if (m_len == 0)
|
||||
{
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m_len++;
|
||||
do {
|
||||
m_len = m_len*2 + GETBIT(bb, src, ilen);
|
||||
} while(!GETBIT(bb, src, ilen));
|
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m_len += 2;
|
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}
|
||||
m_len += (m_off > 0xd00);
|
||||
{
|
||||
const uint8_t *m_pos;
|
||||
m_pos = dst + olen - m_off;
|
||||
dst[olen++] = *m_pos++;
|
||||
do {
|
||||
dst[olen++] = *m_pos++;
|
||||
} while(--m_len > 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
// dump_mem(dst, dst+0x100);
|
||||
#if CONFIG_USE_INIT
|
||||
printk_debug("linxbios_ram.bin length = %08x\r\n", olen);
|
||||
#else
|
||||
print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
|
||||
#endif
|
||||
print_debug("Jumping to LinuxBIOS.\r\n");
|
||||
|
||||
if(cpu_reset == 1 ) {
|
||||
__asm__ volatile (
|
||||
"movl $0xffffffff, %ebp\n\t"
|
||||
);
|
||||
}
|
||||
else {
|
||||
__asm__ volatile (
|
||||
"xorl %ebp, %ebp\n\t"
|
||||
);
|
||||
}
|
||||
|
||||
__asm__ volatile (
|
||||
"cli\n\t"
|
||||
"leal _iseg, %edi\n\t"
|
||||
"jmp %edi\n\t"
|
||||
);
|
||||
|
||||
}
|
||||
@@ -453,12 +453,12 @@ static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_AMD, 0x10f80 }, /* CH7-D0 */
|
||||
{ X86_VENDOR_AMD, 0x10fb0 },
|
||||
//AMD_E0_SUPPORT
|
||||
{ X86_VENDOR_AMD, 0x20f50 }, /* SH7-E0*/
|
||||
{ X86_VENDOR_AMD, 0x20f50 }, /* SH8-E0*/
|
||||
{ X86_VENDOR_AMD, 0x20f40 },
|
||||
{ X86_VENDOR_AMD, 0x20f70 },
|
||||
{ X86_VENDOR_AMD, 0x20fc0 }, /* DH7-E0 */ /* DH-E3 */
|
||||
{ X86_VENDOR_AMD, 0x20fc0 }, /* DH8-E0 */ /* DH-E3 */
|
||||
{ X86_VENDOR_AMD, 0x20ff0 },
|
||||
{ X86_VENDOR_AMD, 0x20f10 }, /* JH7-E0 */
|
||||
{ X86_VENDOR_AMD, 0x20f10 }, /* JH8-E1 */
|
||||
{ X86_VENDOR_AMD, 0x20f30 },
|
||||
{ X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 */
|
||||
{ X86_VENDOR_AMD, 0x20f71 },
|
||||
|
||||
Reference in New Issue
Block a user