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Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51

Browse Source 
Creator:  Yinghai Lu <yhlu@tyan.com>

cache_as_ram for AMD and some intel


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical)
2005-07-06 17:17:25 +00:00
parent b2ed53dd56
commit 6ca7636c8f
84 changed files with 5865 additions and 387 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/i386/include/arch/cpu.h
View File

@ -104,7 +104,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
#define X86_VENDOR_SIS 10
#define X86_VENDOR_UNKNOWN 0xff
#ifndef __ROMCC__
#if !defined( __ROMCC__ ) && defined( __GNUC__)
#include <device/device.h>

8
src/arch/i386/include/arch/hlt.h
View File

@ -1,19 +1,15 @@
#ifndef ARCH_HLT_H
#define ARCH_HLT_H
#ifdef __ROMCC__
#if defined( __ROMCC__) && !defined(__GNUC__)
static void hlt(void)
{
__builtin_hlt();
}
#endif
#if defined(__GNUC__) && !defined(__ROMCC__)
#else
static inline void hlt(void)
{
asm("hlt");
return;
}
#endif

6
src/arch/i386/include/arch/io.h
View File

@ -9,8 +9,7 @@
* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
* versions of the single-IO instructions (inb_p/inw_p/..).
*/
#ifdef __ROMCC__
#if defined( __ROMCC__ ) && !defined (__GNUC__)
static inline void outb(uint8_t value, uint16_t port)
{
__builtin_outb(value, port);
@ -42,7 +41,6 @@ static inline uint32_t inl(uint16_t port)
{
return __builtin_inl(port);
}
#else
static inline void outb(uint8_t value, uint16_t port)
@ -81,7 +79,7 @@ static inline uint32_t inl(uint16_t port)
return value;
}
#endif /* __ROMCC__ */
#endif /* __ROMCC__ && !__GNUC__*/
static inline void outsb(uint16_t port, const void *addr, unsigned long count)
{

29
src/arch/i386/include/arch/romcc_io.h
View File

@ -33,8 +33,7 @@ static inline void write32(unsigned long addr, uint32_t value)
{
*((volatile uint32_t *)(addr)) = value;
}
#if 0
typedef __builtin_div_t div_t;
typedef __builtin_ldiv_t ldiv_t;
typedef __builtin_udiv_t udiv_t;
@ -72,6 +71,32 @@ inline int log2(int value)
*/
return __builtin_bsr(value);
}
#endif
static inline int log2(int value)
{
unsigned int r = 0;
__asm__ volatile (
"bsrl %1, %0\n\t"
"jnz 1f\n\t"
"movl $-1, %0\n\t"
"1:\n\t"
: "=r" (r) : "r" (value));
return r;
}
static inline int log2f(int value)
{
unsigned int r = 0;
__asm__ volatile (
"bsfl %1, %0\n\t"
"jnz 1f\n\t"
"movl $-1, %0\n\t"
"1:\n\t"
: "=r" (r) : "r" (value));
return r;
}
#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
(((BUS) & 0xFF) << 16) | \

3
src/arch/i386/init/crt0.S.lb
View File

@ -37,6 +37,7 @@
#include "crt0_includes.h"
#if USE_DCACHE_RAM == 0
#ifndef CONSOLE_DEBUG_TX_STRING
/* uses: esp, ebx, ax, dx */
# define __CRT_CONSOLE_TX_STRING(string) \
@ -219,3 +220,5 @@ str_pre_main: .string "Jumping to LinuxBIOS.\r\n"
.previous
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
#endif /* USE_DCACHE_RAM */

1
src/arch/i386/init/ldscript.lb
View File

@ -46,6 +46,7 @@ SECTIONS
_rom = .;
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
. = ALIGN(16);
_erom = .;
}

7
src/arch/i386/lib/Config.lb
View File

@ -1,6 +1,13 @@
uses CONFIG_USE_INIT
object c_start.S
object cpu.c
object pci_ops_conf1.c
object pci_ops_conf2.c
object pci_ops_auto.c
object exception.c
if CONFIG_USE_INIT
initobject printk_init.o
end

5
src/arch/i386/lib/c_start.S
View File

@ -15,9 +15,10 @@ _start:
movl %eax, %fs
movl %eax, %gs
intel_chip_post_macro(0x13) /* post 12 */
intel_chip_post_macro(0x13) /* post 13 */
/** clear stack */
cld
leal _stack, %edi
movl $_estack, %ecx
subl %edi, %ecx
@ -80,7 +81,7 @@ _start:
call hardwaremain
/*NOTREACHED*/
.Lhlt:
intel_chip_post_macro(0xee) /* post fe */
intel_chip_post_macro(0xee) /* post ee */
hlt
jmp .Lhlt

108
src/arch/i386/lib/console.c
View File

@ -1,5 +1,6 @@
#include <console/loglevel.h>
#if CONFIG_USE_INIT == 0
static void __console_tx_byte(unsigned char byte)
{
uart_tx_byte(byte);
@ -120,7 +121,7 @@ static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW,
static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
/* Non inline versions.... */
#if 0
static void print_alert_char_(unsigned char value) NOINLINE { print_alert_char(value); }
static void print_alert_hex8_(unsigned char value) NOINLINE { print_alert_hex8(value); }
static void print_alert_hex16_(unsigned short value) NOINLINE { print_alert_hex16(value); }
@ -168,6 +169,111 @@ static void print_spew_hex8_(unsigned char value) NOINLINE { print_spew_hex8(v
static void print_spew_hex16_(unsigned short value) NOINLINE { print_spew_hex16(value); }
static void print_spew_hex32_(unsigned int value) NOINLINE { print_spew_hex32(value); }
static void print_spew_(const char *str) NOINLINE { print_spew(str); }
#endif
#else
extern int do_printk(int msg_level, const char *fmt, ...);
#define printk_emerg(fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
#define printk_alert(fmt, arg...) do_printk(BIOS_ALERT ,fmt, ##arg)
#define printk_crit(fmt, arg...) do_printk(BIOS_CRIT ,fmt, ##arg)
#define printk_err(fmt, arg...) do_printk(BIOS_ERR ,fmt, ##arg)
#define printk_warning(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg)
#define printk_notice(fmt, arg...) do_printk(BIOS_NOTICE ,fmt, ##arg)
#define printk_info(fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg)
#define printk_debug(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg)
#define printk_spew(fmt, arg...) do_printk(BIOS_SPEW ,fmt, ##arg)
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_EMERG
#undef printk_emerg
#define printk_emerg(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ALERT
#undef printk_alert
#define printk_alart(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_CRIT
#undef printk_crit
#define printk_crit(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_ERR
#undef printk_err
#define printk_err(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_WARNING
#undef printk_warning
#define printk_warning(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
#undef printk_notice
#define printk_notice(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_INFO
#undef printk_info
#define printk_info(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
#undef printk_debug
#define printk_debug(fmt, arg...) do {} while(0)
#endif
#if MAXIMUM_CONSOLE_LOGLEVEL <= BIOS_SPEW
#undef printk_spew
#define printk_spew(fmt, arg...) do {} while(0)
#endif
#define print_emerg(STR) printk_emerg ("%s", (STR))
#define print_alert(STR) printk_alert ("%s", (STR))
#define print_crit(STR) printk_crit ("%s", (STR))
#define print_err(STR) printk_err ("%s", (STR))
#define print_warning(STR) printk_warning("%s", (STR))
#define print_notice(STR) printk_notice ("%s", (STR))
#define print_info(STR) printk_info ("%s", (STR))
#define print_debug(STR) printk_debug ("%s", (STR))
#define print_spew(STR) printk_spew ("%s", (STR))
#define print_emerg_char(CH) printk_emerg ("%c", (CH))
#define print_alert_char(CH) printk_alert ("%c", (CH))
#define print_crit_char(CH) printk_crit ("%c", (CH))
#define print_err_char(CH) printk_err ("%c", (CH))
#define print_warning_char(CH) printk_warning("%c", (CH))
#define print_notice_char(CH) printk_notice ("%c", (CH))
#define print_info_char(CH) printk_info ("%c", (CH))
#define print_debug_char(CH) printk_debug ("%c", (CH))
#define print_spew_char(CH) printk_spew ("%c", (CH))
#define print_emerg_hex8(HEX) printk_emerg ("%02x", (HEX))
#define print_alert_hex8(HEX) printk_alert ("%02x", (HEX))
#define print_crit_hex8(HEX) printk_crit ("%02x", (HEX))
#define print_err_hex8(HEX) printk_err ("%02x", (HEX))
#define print_warning_hex8(HEX) printk_warning("%02x", (HEX))
#define print_notice_hex8(HEX) printk_notice ("%02x", (HEX))
#define print_info_hex8(HEX) printk_info ("%02x", (HEX))
#define print_debug_hex8(HEX) printk_debug ("%02x", (HEX))
#define print_spew_hex8(HEX) printk_spew ("%02x", (HEX))
#define print_emerg_hex16(HEX) printk_emerg ("%04x", (HEX))
#define print_alert_hex16(HEX) printk_alert ("%04x", (HEX))
#define print_crit_hex16(HEX) printk_crit ("%04x", (HEX))
#define print_err_hex16(HEX) printk_err ("%04x", (HEX))
#define print_warning_hex16(HEX) printk_warning("%04x", (HEX))
#define print_notice_hex16(HEX) printk_notice ("%04x", (HEX))
#define print_info_hex16(HEX) printk_info ("%04x", (HEX))
#define print_debug_hex16(HEX) printk_debug ("%04x", (HEX))
#define print_spew_hex16(HEX) printk_spew ("%04x", (HEX))
#define print_emerg_hex32(HEX) printk_emerg ("%08x", (HEX))
#define print_alert_hex32(HEX) printk_alert ("%08x", (HEX))
#define print_crit_hex32(HEX) printk_crit ("%08x", (HEX))
#define print_err_hex32(HEX) printk_err ("%08x", (HEX))
#define print_warning_hex32(HEX) printk_warning("%08x", (HEX))
#define print_notice_hex32(HEX) printk_notice ("%08x", (HEX))
#define print_info_hex32(HEX) printk_info ("%08x", (HEX))
#define print_debug_hex32(HEX) printk_debug ("%08x", (HEX))
#define print_spew_hex32(HEX) printk_spew ("%08x", (HEX))
#endif /* CONFIG_USE_INIT == 0 */
#ifndef LINUXBIOS_EXTRA_VERSION
#define LINUXBIOS_EXTRA_VERSION ""

46
src/arch/i386/lib/printk_init.c Normal file
View File

@ -0,0 +1,46 @@
/*
* blantantly copied from linux/kernel/printk.c
*
* Copyright (C) 1991, 1992 Linus Torvalds
*
* by yhlu moved from arch/ppc/lib/printk_init.c, removed the global variable console_loglevel
*/
#include <stdarg.h>
#include <console/loglevel.h>
/* printk's without a loglevel use this.. */
#define DEFAULT_MESSAGE_LOGLEVEL 4 /* BIOS_WARNING */
/* Keep together for sysctl support */
/* Using an global varible can cause problem when we reset the stack from cache as ram to ram*/
#if 0
int console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
#else
#define console_loglevel ASM_CONSOLE_LOGLEVEL
#endif
extern int vtxprintf(void (*)(unsigned char), const char *, va_list);
extern void uart8250_tx_byte(unsigned, unsigned char);
void console_tx_byte(unsigned char byte)
{
if (byte == '\n')
uart8250_tx_byte(TTYS0_BASE, '\r');
uart8250_tx_byte(TTYS0_BASE, byte);
}
int do_printk(int msg_level, const char *fmt, ...)
{
va_list args;
int i;
if (msg_level >= console_loglevel) {
return 0;
}
va_start(args, fmt);
i = vtxprintf(console_tx_byte, fmt, args);
va_end(args);
return i;
}

17
src/config/Config.lb
View File

@ -63,12 +63,29 @@ makerule linuxbios_ram.rom
action "cp $(LINUXBIOS_RAM-1) linuxbios_ram.rom"
end
if CONFIG_USE_INIT
makerule init.o
depends "$(INIT-OBJECTS)"
action "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
end
makerule linuxbios
depends "crt0.o init.o linuxbios_ram.rom ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
end
else
makerule linuxbios
depends "crt0.o $(INIT-OBJECTS) linuxbios_ram.rom ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
end
end
makerule linuxbios.a
depends "$(OBJECTS)"
action "rm -f linuxbios.a"

4
src/config/Options.lb
View File

@ -164,7 +164,7 @@ define CONFIG_CHIP_CONFIGURE
end
define CONFIG_USE_INIT
default 0
export used
export always
comment "Use stage 1 initialization code"
end
@ -270,7 +270,7 @@ define _RAMSTART
end
define USE_DCACHE_RAM
default 0
export used
export always
comment "Use data cache as temporary RAM if possible"
end
define DCACHE_RAM_BASE

220
src/cpu/amd/car/cache_as_ram.inc Normal file
View File

@ -0,0 +1,220 @@
/* by yhlu 6.2005 */
/* We will use 4K bytes only */
#define CacheSize DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
/* Save the BIST result */
movl %eax, %ebp
CacheAsRam:
/* hope we can skip the double set for normal part */
#if USE_FALLBACK_IMAGE == 1
/* Set MtrrFixDramModEn for clear fixed mtrr */
xorl %eax, %eax # clear %eax and %edx
xorl %edx, %edx
enable_fixed_mtrr_dram_modify:
movl $SYSCFG_MSR, %ecx
rdmsr
andl $(~(SYSCFG_MSR_MtrrFixDramEn|SYSCFG_MSR_MtrrVarDramEn)), %eax
orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
wrmsr
/* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */
movl $0x00000c00, %eax
wrmsr
/*Clear all MTRRs */
xorl %edx, %edx
movl $fixed_mtrr_msr, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
testl %eax, %eax
jz clear_fixed_var_mtrr_out
movl %eax, %ecx
xorl %eax, %eax
wrmsr
jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:
/* Enable the MTRRs and IORRs in SYSCFG */
movl $SYSCFG_MSR, %ecx
rdmsr
orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
wrmsr
#if 1
#if CacheSize == 0x10000
/* enable caching for 64K using fixed mtrr */
movl $0x268, %ecx /* fix4k_c0000*/
movl $0x06060606, %eax /* WB IO type */
movl %eax, %edx
wrmsr
movl $0x269, %ecx
wrmsr
#endif
#if CacheSize == 0x8000
/* enable caching for 32K using fixed mtrr */
movl $0x269, %ecx /* fix4k_c8000*/
movl $0x06060606, %eax /* WB IO type */
movl %eax, %edx
wrmsr
#endif
/* enable caching for 16K/8K/4K using fixed mtrr */
movl $0x269, %ecx /* fix4k_cc000*/
#if CacheSize == 0x4000
movl $0x06060606, %edx /* WB IO type */
#endif
#if CacheSize == 0x2000
movl $0x06060000, %edx /* WB IO type */
#endif
#if CacheSize == 0x1000
movl $0x06000000, %edx /* WB IO type */
#endif
xorl %eax, %eax
wrmsr
#else
/* enable caching for 64K using variable mtrr */
movl $0x200, %ecx
xorl %edx, %edx
movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $0x201, %ecx
movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
movl $((~((CacheBase + CacheSize) - 1)) | 0x800), %eax
wrmsr
/* make it to be IO by clearing RD Dram and WR Dram */
movl $IORR0_BASE, %ecx
xorl %edx, %edx
movl $CacheBase, %eax /* bit 3, and bit 4 = 0 mean clear RD ram and WR ram */
wrmsr
movl $IORR0_MASK, %ecx
movl $0x000000ff, %edx
movl $(~((CacheBase + CacheSize) - 1) | 0x800), %eax
wrmsr
#endif
/* enable memory access for 0 - 1MB using top_mem */
movl $TOP_MEM, %ecx
xorl %edx, %edx
movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
#else
/* disable cache */
movl %cr0, %eax
orl $(0x1<<30),%eax
movl %eax, %cr0
#endif /* USE_FALLBACK_IMAGE == 1*/
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
/* enable write base caching so we can do execute in place
* on the flash rom.
*/
movl $0x202, %ecx
xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $0x203, %ecx
movl $0x0000000f, %edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
/* enable cache */
movl %cr0, %eax
andl $0x9fffffff,%eax
movl %eax, %cr0
#if USE_FALLBACK_IMAGE == 1
/* Read the range with lodsl*/
movl $(CacheBase+CacheSize-4), %esi
std
movl $(CacheSize>>2), %ecx
rep lodsl
/* Clear the range */
movl $(CacheBase+CacheSize-4), %edi
movl $(CacheSize>>2), %ecx
xorl %eax, %eax
rep stosl
#if 0
/* check the cache as ram */
movl $CacheBase, %esi
movl $(CacheSize>>2), %ecx
.xin1:
movl %esi, %eax
movl %eax, (%esi)
movl $0x1000, %edx
movb %ah, %al
.testx1:
outb %al, $0x80
decl %edx
jnz .testx1
movl (%esi), %eax
cmpb 0xff, %al
je .xin2 /* dont show */
movl $0x1000, %edx
.testx2:
outb %al, $0x80
decl %edx
jnz .testx2
.xin2: decl %ecx
je .xout1
add $4, %esi
jmp .xin1
.xout1:
#endif
#endif /*USE_FALLBACK_IMAGE == 1*/
movl $(CacheBase+CacheSize-4), %eax
movl %eax, %esp
/* Restore the BIST result */
movl %ebp, %eax
/* We need to set ebp ? No need */
movl %esp, %ebp
pushl %eax /* bist */
call amd64_main
/* We will not go back */
fixed_mtrr_msr:
.long 0x250, 0x258, 0x259
.long 0x268, 0x269, 0x26A
.long 0x26B, 0x26C, 0x26D
.long 0x26E, 0x26F
var_mtrr_msr:
.long 0x200, 0x201, 0x202, 0x203
.long 0x204, 0x205, 0x206, 0x207
.long 0x208, 0x209, 0x20A, 0x20B
.long 0x20C, 0x20D, 0x20E, 0x20F
var_iorr_msr:
.long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
mem_top:
.long 0xC001001A, 0xC001001D
.long 0x000 /* NULL, end of table */
.CacheAsRam_out:

17
src/cpu/amd/car/cache_as_ram.lds Normal file
View File

@ -0,0 +1,17 @@
/*
* init sections to place code running with cache as ram.
*
* 2004 by Stefan Reinauer <stepan@openbios.org>
*/
SECTIONS {
.init . : {
_init = .;
*(.init.text);
*(.init.rodata);
*(.init.rodata.*);
. = ALIGN(16);
_einit = .;
}
}

94
src/cpu/amd/car/cache_as_ram_post.c Normal file
View File

@ -0,0 +1,94 @@
/* by yhlu 6.2005 */
__asm__ volatile (
/*
FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
It is only needed if we want to go back
*/
/* We don't need cache as ram for now on */
/* disable cache */
"movl %cr0, %eax\n\t"
"orl $(0x1<<30),%eax\n\t"
"movl %eax, %cr0\n\t"
/* clear sth */
"movl $0x269, %ecx\n\t" /* fix4k_c8000*/
"xorl %edx, %edx\n\t"
"xorl %eax, %eax\n\t"
"wrmsr\n\t"
#if DCACHE_RAM_SIZE > 0x8000
"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
"wrmsr\n\t"
#endif
/* disable fixed mtrr from now on, it will be enabled by linuxbios_ram again*/
"movl $0xC0010010, %ecx\n\t"
// "movl $SYSCFG_MSR, %ecx\n\t"
"rdmsr\n\t"
"andl $(~(3<<18)), %eax\n\t"
// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
"wrmsr\n\t"
/* Set the default memory type and disable fixed and enable variable MTRRs */
"movl $0x2ff, %ecx\n\t"
// "movl $MTRRdefType_MSR, %ecx\n\t"
"xorl %edx, %edx\n\t"
/* Enable Variable and Disable Fixed MTRRs */
"movl $0x00000800, %eax\n\t"
"wrmsr\n\t"
#if defined(CLEAR_FIRST_1M_RAM)
/* enable caching for first 1M using variable mtrr */
"movl $0x200, %ecx\n\t"
"xorl %edx, %edx\n\t"
"movl $(0 | 1), %eax\n\t"
// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
"wrmsr\n\t"
"movl $0x201, %ecx\n\t"
"movl $0x0000000f, %edx\n\t"
"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
"wrmsr\n\t"
#endif
/* enable cache */
"movl %cr0, %eax\n\t"
"andl $0x9fffffff,%eax\n\t"
"movl %eax, %cr0\n\t"
#if defined(CLEAR_FIRST_1M_RAM)
/* clear the first 1M */
"movl $0x0, %edi\n\t"
"cld\n\t"
"movl $(0x100000>>2), %ecx\n\t"
"xorl %eax, %eax\n\t"
"rep stosl\n\t"
/* disable cache */
"movl %cr0, %eax\n\t"
"orl $(0x1<<30),%eax\n\t"
"movl %eax, %cr0\n\t"
/* enable caching for first 1M using variable mtrr */
"movl $0x200, %ecx\n\t"
"xorl %edx, %edx\n\t"
"movl $(0 | 6), %eax\n\t"
// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
"wrmsr\n\t"
"movl $0x201, %ecx\n\t"
"movl $0x0000000f, %edx\n\t"
"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
"wrmsr\n\t"
/* enable cache */
"movl %cr0, %eax\n\t"
"andl $0x9fffffff,%eax\n\t"
"movl %eax, %cr0\n\t"
"invd\n\t"
/*
FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back
But the problem is the range is some io related, So don't go back
*/
#endif
);

132
src/cpu/amd/car/copy_and_run.c Normal file
View File

@ -0,0 +1,132 @@
/* by yhlu 6.2005
moved from nrv2v.c and some lines from crt0.S
*/
#ifndef ENDIAN
#define ENDIAN 0
#endif
#ifndef BITSIZE
#define BITSIZE 32
#endif
#define GETBIT_8(bb, src, ilen) \
(((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1)
#define GETBIT_LE16(bb, src, ilen) \
(bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1))
#define GETBIT_LE32(bb, src, ilen) \
(bc > 0 ? ((bb>>--bc)&1) : (bc=31,\
bb=*(const uint32_t *)((src)+ilen),ilen+=4,(bb>>31)&1))
#if ENDIAN == 0 && BITSIZE == 8
#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen)
#endif
#if ENDIAN == 0 && BITSIZE == 16
#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen)
#endif
#if ENDIAN == 0 && BITSIZE == 32
#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
#endif
static void copy_and_run(unsigned cpu_reset)
{
uint8_t *src, *dst;
unsigned long dst_len;
unsigned long ilen = 0, olen = 0, last_m_off = 1;
uint32_t bb = 0;
unsigned bc = 0;
print_debug("Copying LinuxBIOS to ram.\r\n");
#if !CONFIG_COMPRESS
__asm__ volatile (
"leal _liseg, %0\n\t"
"leal _iseg, %1\n\t"
"leal _eiseg, %2\n\t"
"subl %1, %2\n\t"
: "=a" (src), "=b" (dst), "=c" (dst_len)
);
memcpy(src, dst, dst_len);
#else
__asm__ volatile (
"leal 4+_liseg, %0\n\t"
"leal _iseg, %1\n\t"
: "=a" (src) , "=b" (dst)
);
#if CONFIG_USE_INIT
printk_debug("src=%08x\r\n",src);
printk_debug("dst=%08x\r\n",dst);
#else
print_debug("src="); print_debug_hex32(src); print_debug("\r\n");
print_debug("dst="); print_debug_hex32(dst); print_debug("\r\n");
#endif
for(;;) {
unsigned int m_off, m_len;
while(GETBIT(bb, src, ilen)) {
dst[olen++] = src[ilen++];
}
m_off = 1;
do {
m_off = m_off*2 + GETBIT(bb, src, ilen);
} while (!GETBIT(bb, src, ilen));
if (m_off == 2)
{
m_off = last_m_off;
}
else
{
m_off = (m_off - 3)*256 + src[ilen++];
if(m_off == 0xffffffffU)
break;
last_m_off = ++m_off;
}
m_len = GETBIT(bb, src, ilen);
m_len = m_len*2 + GETBIT(bb, src, ilen);
if (m_len == 0)
{
m_len++;
do {
m_len = m_len*2 + GETBIT(bb, src, ilen);
} while(!GETBIT(bb, src, ilen));
m_len += 2;
}
m_len += (m_off > 0xd00);
{
const uint8_t *m_pos;
m_pos = dst + olen - m_off;
dst[olen++] = *m_pos++;
do {
dst[olen++] = *m_pos++;
} while(--m_len > 0);
}
}
#endif
// dump_mem(dst, dst+0x100);
#if CONFIG_USE_INIT
printk_debug("linxbios_ram.bin length = %08x\r\n", olen);
#else
print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
#endif
print_debug("Jumping to LinuxBIOS.\r\n");
if(cpu_reset == 1 ) {
__asm__ volatile (
"movl $0xffffffff, %ebp\n\t"
);
}
else {
__asm__ volatile (
"xorl %ebp, %ebp\n\t"
);
}
__asm__ volatile (
"cli\n\t"
"leal _iseg, %edi\n\t"
"jmp %edi\n\t"
);
}

6
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -453,12 +453,12 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x10f80 }, /* CH7-D0 */
{ X86_VENDOR_AMD, 0x10fb0 },
//AMD_E0_SUPPORT
{ X86_VENDOR_AMD, 0x20f50 }, /* SH7-E0*/
{ X86_VENDOR_AMD, 0x20f50 }, /* SH8-E0*/
{ X86_VENDOR_AMD, 0x20f40 },
{ X86_VENDOR_AMD, 0x20f70 },
{ X86_VENDOR_AMD, 0x20fc0 }, /* DH7-E0 */ /* DH-E3 */
{ X86_VENDOR_AMD, 0x20fc0 }, /* DH8-E0 */ /* DH-E3 */
{ X86_VENDOR_AMD, 0x20ff0 },
{ X86_VENDOR_AMD, 0x20f10 }, /* JH7-E0 */
{ X86_VENDOR_AMD, 0x20f10 }, /* JH8-E1 */
{ X86_VENDOR_AMD, 0x20f30 },
{ X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 */
{ X86_VENDOR_AMD, 0x20f71 },

192
src/cpu/x86/car/cache_as_ram.inc Normal file
View File

@ -0,0 +1,192 @@
/* We will use 4K bytes only */
#define CacheSize DCACHE_RAM_SIZE
#define CacheBase DCACHE_RAM_BASE
#include <cpu/x86/mtrr.h>
/* Save the BIST result */
movl %eax, %ebp
CacheAsRam:
/* hope we can skip the double set for normal part */
#if USE_FALLBACK_IMAGE == 1
/*Clear all MTRRs */
xorl %edx, %edx
movl $fixed_mtrr_msr, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
testl %eax, %eax
jz clear_fixed_var_mtrr_out
movl %eax, %ecx
xorl %eax, %eax
wrmsr
jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:
/* enable caching for 64K using variable mtrr */
movl $0x200, %ecx
xorl %edx, %edx
movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $0x201, %ecx
movl $0x0000000f, %edx
movl $((~((CacheBase + CacheSize) - 1)) | 0x800), %eax
wrmsr
/* Set the default memory type and enable variable MTRRs */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
/* Enable Variable MTRRs */
movl $0x00000800, %eax
wrmsr
/* Disable fast string operation */
movl $0x1a0, %ecx
rdmsr
andl $(~0x1), %eax
wrmsr
#else
/* disable cache */
movl %cr0, %eax
orl $(0x1<<30),%eax
movl %eax, %cr0
#endif /* USE_FALLBACK_IMAGE == 1*/
#if 0
#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
/* enable write base caching so we can do execute in place
* on the flash rom.
*/
movl $0x202, %ecx
xorl %edx, %edx
movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
wrmsr
movl $0x203, %ecx
movl $0x0000000f, %edx
movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
#endif
/* enable cache */
movl %cr0, %eax
andl $0x9fffffff,%eax
movl %eax, %cr0
#if USE_FALLBACK_IMAGE == 1
// intel_chip_post_macro(0x11) /* post 11 */
/* Read the range with lodsl*/
movl $CacheBase, %esi
cld
movl $(CacheSize>>2), %ecx
rep lodsl
// Disable the cache. This is the trick. Processors
// Pentium Pro and above are designed to respond to cache
// hits with CD=1 and NW=1. That is read hits access the
// cache; write hits update the cache. With the tags
// established above and no snoop hit, the cache will
// behave as RAM.
movl %cr0, %eax
orl $0x60000000, %eax
movl %eax, %cr0
/* Clear the range */
movl $CacheBase, %edi
cld
movl $(CacheSize>>2), %ecx
xorl %eax, %eax
rep stosl
#if 1
/* check the cache as ram */
movl $CacheBase, %esi
movl $(CacheSize>>2), %ecx
.xin1:
movl %esi, %eax
movl %eax, (%esi)
decl %ecx
je .xout1
add $4, %esi
jmp .xin1
.xout1:
movl $CacheBase, %esi
// movl $(CacheSize>>2), %ecx
movl $4, %ecx
.xin1x:
movl %esi, %eax
movl $0x4000, %edx
movb %ah, %al
.testx1:
outb %al, $0x80
decl %edx
jnz .testx1
movl (%esi), %eax
cmpb 0xff, %al
je .xin2 /* dont show */
movl $0x4000, %edx
.testx2:
outb %al, $0x80
decl %edx
jnz .testx2
.xin2: decl %ecx
je .xout1x
add $4, %esi
jmp .xin1x
.xout1x:
#endif
#endif /*USE_FALLBACK_IMAGE == 1*/
// intel_chip_post_macro(0x12) /* post 12 */
movl $(CacheBase+CacheSize-4), %eax
movl %eax, %esp
/* Load a different set of data segments */
#if CONFIG_USE_INIT
movw $CACHE_RAM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
#endif
lout:
// intel_chip_post_macro(0x13) /* post 13 */
/* Restore the BIST result */
movl %ebp, %eax
/* We need to set ebp ? No need */
movl %esp, %ebp
pushl %eax /* bist */
call amd64_main
/* We will not go back */
fixed_mtrr_msr:
.long 0x250, 0x258, 0x259
.long 0x268, 0x269, 0x26A
.long 0x26B, 0x26C, 0x26D
.long 0x26E, 0x26F
var_mtrr_msr:
.long 0x200, 0x201, 0x202, 0x203
.long 0x204, 0x205, 0x206, 0x207
.long 0x208, 0x209, 0x20A, 0x20B
.long 0x20C, 0x20D, 0x20E, 0x20F
.long 0x000 /* NULL, end of table */
.CacheAsRam_out:

11
src/cpu/x86/car/cache_as_ram.lds Normal file
View File

@ -0,0 +1,11 @@
SECTIONS {
.init . : {
_init = .;
*(.init.text);
*(.init.rodata);
*(.init.rodata.*);
. = ALIGN(16);
_einit = .;
}
}

82
src/cpu/x86/car/cache_as_ram_post.c Normal file
View File

@ -0,0 +1,82 @@
__asm__ volatile (
/*
FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
It is only needed if we want to go back
*/
/* We don't need cache as ram for now on */
/* disable cache */
"movl %cr0, %eax\n\t"
"orl $(0x1<<30),%eax\n\t"
"movl %eax, %cr0\n\t"
/* clear sth */
"movl $0x200, %ecx\n\t"
"xorl %edx, %edx\n\t"
"xorl %eax, %eax\n\t"
"wrmsr\n\t"
"movl $0x201, %ecx\n\t"
"wrmsr\n\t"
/* enable fast string operation */
"movl $0x1a0, %ecx\n\t"
"rdmsr\n\t"
"orl $1, %eax\n\t"
"wrmsr\n\t"
#if defined(CLEAR_FIRST_1M_RAM)
/* enable caching for first 1M using variable mtrr */
"movl $0x200, %ecx\n\t"
"xorl %edx, %edx\n\t"
"movl $(0 | 1), %eax\n\t"
// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
"wrmsr\n\t"
"movl $0x201, %ecx\n\t"
"movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
"wrmsr\n\t"
#endif
/* enable cache */
"movl %cr0, %eax\n\t"
"andl $0x9fffffff,%eax\n\t"
"movl %eax, %cr0\n\t"
#if defined(CLEAR_FIRST_1M_RAM)
/* clear the first 1M */
"movl $0x0, %edi\n\t"
"cld\n\t"
"movl $(0x100000>>2), %ecx\n\t"
"xorl %eax, %eax\n\t"
"rep stosl\n\t"
/* disable cache */
"movl %cr0, %eax\n\t"
"orl $(0x1<<30),%eax\n\t"
"movl %eax, %cr0\n\t"
/* enable caching for first 1M using variable mtrr */
"movl $0x200, %ecx\n\t"
"xorl %edx, %edx\n\t"
"movl $(0 | 6), %eax\n\t"
// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
"wrmsr\n\t"
"movl $0x201, %ecx\n\t"
"movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
"wrmsr\n\t"
/* enable cache */
"movl %cr0, %eax\n\t"
"andl $0x9fffffff,%eax\n\t"
"movl %eax, %cr0\n\t"
"invd\n\t"
/*
FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back
But the problem is the range is some io related, So don't go back
*/
#endif
);

132
src/cpu/x86/car/copy_and_run.c Normal file
View File

@ -0,0 +1,132 @@
/* by yhlu 6.2005
moved from nrv2v.c and some lines from crt0.S
*/
#ifndef ENDIAN
#define ENDIAN 0
#endif
#ifndef BITSIZE
#define BITSIZE 32
#endif
#define GETBIT_8(bb, src, ilen) \
(((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1)
#define GETBIT_LE16(bb, src, ilen) \
(bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1))
#define GETBIT_LE32(bb, src, ilen) \
(bc > 0 ? ((bb>>--bc)&1) : (bc=31,\
bb=*(const uint32_t *)((src)+ilen),ilen+=4,(bb>>31)&1))
#if ENDIAN == 0 && BITSIZE == 8
#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen)
#endif
#if ENDIAN == 0 && BITSIZE == 16
#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen)
#endif
#if ENDIAN == 0 && BITSIZE == 32
#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
#endif
static void copy_and_run(unsigned cpu_reset)
{
uint8_t *src, *dst;
unsigned long dst_len;
unsigned long ilen = 0, olen = 0, last_m_off = 1;
uint32_t bb = 0;
unsigned bc = 0;
print_debug("Copying LinuxBIOS to ram.\r\n");
#if !CONFIG_COMPRESS
__asm__ volatile (
"leal _liseg, %0\n\t"
"leal _iseg, %1\n\t"
"leal _eiseg, %2\n\t"
"subl %1, %2\n\t"
: "=a" (src), "=b" (dst), "=c" (dst_len)
);
memcpy(src, dst, dst_len);
#else
__asm__ volatile (
"leal 4+_liseg, %0\n\t"
"leal _iseg, %1\n\t"
: "=a" (src) , "=b" (dst)
);
#if CONFIG_USE_INIT
printk_debug("src=%08x\r\n",src);
printk_debug("dst=%08x\r\n",dst);
#else
print_debug("src="); print_debug_hex32(src); print_debug("\r\n");
print_debug("dst="); print_debug_hex32(dst); print_debug("\r\n");
#endif
for(;;) {
unsigned int m_off, m_len;
while(GETBIT(bb, src, ilen)) {
dst[olen++] = src[ilen++];
}
m_off = 1;
do {
m_off = m_off*2 + GETBIT(bb, src, ilen);
} while (!GETBIT(bb, src, ilen));
if (m_off == 2)
{
m_off = last_m_off;
}
else
{
m_off = (m_off - 3)*256 + src[ilen++];
if(m_off == 0xffffffffU)
break;
last_m_off = ++m_off;
}
m_len = GETBIT(bb, src, ilen);
m_len = m_len*2 + GETBIT(bb, src, ilen);
if (m_len == 0)
{
m_len++;
do {
m_len = m_len*2 + GETBIT(bb, src, ilen);
} while(!GETBIT(bb, src, ilen));
m_len += 2;
}
m_len += (m_off > 0xd00);
{
const uint8_t *m_pos;
m_pos = dst + olen - m_off;
dst[olen++] = *m_pos++;
do {
dst[olen++] = *m_pos++;
} while(--m_len > 0);
}
}
#endif
// dump_mem(dst, dst+0x100);
#if CONFIG_USE_INIT
printk_debug("linxbios_ram.bin length = %08x\r\n", olen);
#else
print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
#endif
print_debug("Jumping to LinuxBIOS.\r\n");
if(cpu_reset == 1 ) {
__asm__ volatile (
"movl $0xffffffff, %ebp\n\t"
);
}
else {
__asm__ volatile (
"xorl %ebp, %ebp\n\t"
);
}
__asm__ volatile (
"cli\n\t"
"leal _iseg, %edi\n\t"
"jmp %edi\n\t"
);
}

2
src/cpu/x86/lapic/boot_cpu.c
View File

@ -1,6 +1,6 @@
#include <cpu/x86/msr.h>
int boot_cpu(void)
static int boot_cpu(void)
{
int bsp;
msr_t msr;

2
src/devices/emulator/x86emu/ops.c
View File

@ -70,7 +70,7 @@
*
****************************************************************************/
#include "x86emu/x86emui.h"
#include "x86emui.h"
/*----------------------------- Implementation ----------------------------*/

127
src/drivers/generic/debug/debug_dev.c
View File

@ -76,26 +76,26 @@ static void print_cpuid()
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.hi);
index, msr.hi, msr.lo);
}
}
static void print_smbus_regs(struct device *dev)
{
int j;
printk_debug("smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link );
printk_debug("%s", dev_path(dev));
printk_debug("smbus: %s[%d]->", dev_path(dev->bus->dev), dev->bus->link);
printk_debug("%s", dev_path(dev));
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
printk_debug("\r\n%02x: ", j);
}
status = smbus_read_byte(dev, j);
if (status < 0) {
printk_debug("bad device status= %08x\r\n", status);
// printk_debug("bad device status= %08x\r\n", status);
break;
}
if ((j & 0xf) == 0) {
printk_debug("\r\n%02x: ", j);
}
byte = status & 0xff;
printk_debug("%02x ", byte);
}
@ -125,9 +125,113 @@ static void print_smbus_regs_all(struct device *dev)
}
}
}
static void print_msr_dualcore(void)
{
msr_t msr;
unsigned index;
unsigned eax, ebx, ecx, edx;
index = 0x80000008;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("cpuid[%08x]: %08x %08x %08x %08x\n",
index, eax, ebx, ecx, edx);
printk_debug("core number %d\n", ecx & 0xff);
index = 0xc001001f;
printk_debug("Reading msr: 0x%08x\n", index);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x bit 54 is %d\n",
index, msr.hi, msr.lo, (msr.hi>> (54-32)) & 1);
#if 0
msr.hi |= (1<<(54-32));
wrmsr(index, msr);
msr = rdmsr(index);
printk_debug("msr[0x%08x]: 0x%08x%08x\n",
index, msr.hi, msr.lo);
#endif
}
static void print_cache_size(void)
{
unsigned index;
unsigned int n, eax, ebx, ecx, edx;
index = 0x80000000;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
n = eax;
if (n >= 0x80000005) {
index = 0x80000005;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
}
if (n >= 0x80000006) {
index = 0x80000006;
printk_debug("calling cpuid 0x%08x\n", index);
asm volatile(
"cpuid"
: "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
: "a" (index)
);
printk_debug("CPU: L2 Cache: %dK (%d bytes/line)\n",
ecx >> 16, ecx & 0xFF);
}
}
struct tsc_struct {
unsigned lo;
unsigned hi;
};
typedef struct tsc_struct tsc_t;
static tsc_t rdtsc(void)
{
tsc_t res;
asm volatile(
"rdtsc"
: "=a" (res.lo), "=d"(res.hi) /* outputs */
);
return res;
}
static void print_tsc(void) {
tsc_t tsc;
tsc = rdtsc();
printk_debug("tsc: 0x%08x%08x\n",
tsc.hi, tsc.lo);
udelay(1);
tsc = rdtsc();
printk_debug("tsc: 0x%08x%08x after udelay(1) \n",
tsc.hi, tsc.lo);
}
static void debug_init(device_t dev)
{
#if CONFIG_CHIP_NAME
device_t parent;
#endif
if (!dev->enabled)
return;
switch(dev->path.u.pnp.device) {
@ -155,6 +259,15 @@ static void debug_init(device_t dev)
case 4:
print_smbus_regs_all(&dev_root);
break;
case 5:
print_msr_dualcore();
break;
case 6:
print_cache_size();
break;
case 7:
print_tsc();
break;
}
}

2
src/include/cpu/amd/mtrr.h
View File

@ -31,7 +31,7 @@
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
#ifndef __ROMCC__
#if !defined( __ROMCC__ ) && !defined (ASSEMBLY)
void amd_setup_mtrrs(void);
#endif /* __ROMCC__ */

5
src/include/cpu/x86/bist.h
View File

@ -4,9 +4,14 @@
static void report_bist_failure(unsigned long bist)
{
if (bist != 0) {
#if CONFIG_USE_INIT
printk_emerg("BIST failed: %08x", bist);
#else
print_emerg("BIST failed: ");
print_emerg_hex32(bist);
#endif
die("\r\n");
}
}

2
src/include/cpu/x86/cache.h
View File

@ -41,7 +41,7 @@ static inline void disable_cache(void)
wbinvd();
}
#ifndef __ROMCC__
#if !defined( __ROMCC__) && defined (__GNUC__)
void x86_enable_cache(void);
#endif /* !__ROMCC__ */

9
src/include/cpu/x86/msr.h
View File

@ -1,8 +1,7 @@
#ifndef CPU_X86_MSR_H
#define CPU_X86_MSR_H
#ifdef __ROMCC__
#if defined( __ROMCC__) && !defined (__GNUC__)
typedef __builtin_msr_t msr_t;
@ -16,9 +15,7 @@ static void wrmsr(unsigned long index, msr_t msr)
__builtin_wrmsr(index, msr.lo, msr.hi);
}
#endif /* __ROMCC__ */
#if defined(__GNUC__) && !defined(__ROMCC__)
#else
typedef struct msr_struct
{
@ -46,7 +43,7 @@ static inline void wrmsr(unsigned index, msr_t msr)
);
}
#endif /* __GNUC__ */
#endif /* ROMCC__ && !__GNUC__ */
#endif /* CPU_X86_MSR_H */

2
src/include/cpu/x86/mtrr.h
View File

@ -32,7 +32,7 @@
#define MTRRfix4K_F8000_MSR 0x26f
#if !defined(__ROMCC__) && !defined(ASSEMBLY)
#if !defined(__ROMCC__) && !defined (ASSEMBLY)
void x86_setup_mtrrs(void);
int x86_mtrr_check(void);

2
src/include/delay.h
View File

@ -1,6 +1,6 @@
#ifndef DELAY_H
#define DELAY_H
#ifndef __ROMCC__
#if !defined( __ROMCC__) && defined (__GNUC__)
void udelay(unsigned usecs);
void mdelay(unsigned msecs);

4
src/lib/Config.lb
View File

@ -19,7 +19,7 @@ makedefine .PHONY : version.o
if CONFIG_USE_INIT
initobject uart8250.c
initobject memset.o
# initobject memset.o
initobject memcpy.o
initobject memcmp.o
# initobject memcmp.o
end

2
src/mainboard/Iwill/DK8S2/Options.lb
View File

@ -51,6 +51,8 @@ uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_USE_INIT
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288

2
src/mainboard/Iwill/DK8X/Options.lb
View File

@ -51,6 +51,8 @@ uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_USE_INIT
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE=524288

2
src/mainboard/amd/quartet/Options.lb
View File

@ -47,6 +47,8 @@ uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_USE_INIT
###
### Build options

2
src/mainboard/amd/serenade/Options.lb
View File

@ -47,6 +47,8 @@ uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_USE_INIT
###
### Build options
###

2
src/mainboard/amd/solo/Options.lb
View File

@ -48,6 +48,8 @@ uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_USE_INIT
###
### Build options

2
src/mainboard/arima/hdama/Options.lb
View File

@ -53,6 +53,8 @@ uses OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_USE_INIT
###
### Build options
###

2
src/mainboard/ibm/e325/Options.lb
View File

@ -47,6 +47,8 @@ uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_USE_INIT
###
### Build options

2
src/mainboard/island/aruma/Options.lb
View File

@ -53,6 +53,8 @@ uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_USE_INIT
###
### Build options
###

2
src/mainboard/newisys/khepri/Options.lb
View File

@ -47,6 +47,8 @@ uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_USE_INIT
###
### Build options
###

161
src/mainboard/tyan/s2735/Config.lb
View File

@ -16,6 +16,7 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -34,6 +35,7 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end
##
## Build the objects we have code for in this directory.
##
@ -42,7 +44,26 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
@ -66,13 +87,24 @@ makerule ./auto.inc
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/intel/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
@ -85,8 +117,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
@ -94,23 +129,40 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/intel/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
# ROMCC
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
@ -118,15 +170,16 @@ mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files
##
dir /pc80
if CONFIG_CHIP_NAME
config chip.h
end
# sample config for tyan/s2735
chip northbridge/intel/e7501
device pci_domain 0 on
@ -135,7 +188,12 @@ chip northbridge/intel/e7501
device pci 2.0 on
chip southbridge/intel/i82870
device pci 1c.0 on end
device pci 1d.0 on end
device pci 1d.0 on
chip drivers/pci/onboard
device pci 1.0 on end # intel lan
device pci 1.1 on end
end
end
device pci 1e.0 on end
device pci 1f.0 on end
end
@ -147,42 +205,55 @@ chip northbridge/intel/e7501
device pci 1d.2 on end
device pci 1d.3 on end
device pci 1d.7 on end
device pci 1e.0 on end
device pci 1e.0 on
chip drivers/pci/onboard
device pci 1.0 on end # intel lan 10/100
end
chip drivers/pci/onboard
device pci 2.0 on end # ati
end
end
device pci 1f.0 on
# device pci 8.0 end
chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
end
end
chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
irq 0x70 = 5
end
end
end
device pci 1f.1 off end
device pci 1f.2 on end

73
src/mainboard/tyan/s2735/Options.lb
View File

@ -9,7 +9,9 @@ uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses SERIAL_CPU_INIT
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
@ -33,8 +35,15 @@ uses LB_CKS_LOC
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses LINUXBIOS_EXTRA_VERSION
uses _RAMBASE
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
@ -44,31 +53,35 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_CONSOLE_BTEXT
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
###
### Build options
###
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
##
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
#default ROM_SIZE=524288
#512K bytes
default ROM_SIZE=524288
#1M bytes
default ROM_SIZE=1048576
#default ROM_SIZE=1048576
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
default FALLBACK_SIZE=131072
###
### Build options
###
##
## Build code for the fallback boot
##
@ -79,23 +92,21 @@ default HAVE_FALLBACK_BOOT=1
##
default HAVE_HARD_RESET=1
##
## Funky hard reset implementation
##
#default HARD_RESET_BUS=3
#default HARD_RESET_DEVICE=4
#default HARD_RESET_FUNCTION=0
default HARD_RESET_BUS=1
default HARD_RESET_DEVICE=4
default HARD_RESET_FUNCTION=0
## Delay timer options
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
default IRQ_SLOT_COUNT=15
default IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
@ -121,8 +132,28 @@ default LB_CKS_LOC=123
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
default SERIAL_CPU_INIT=0
#BTEXT Console
#default CONFIG_CONSOLE_BTEXT=1
#VGA Console
#default CONFIG_CONSOLE_VGA=1
#default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xF2000000
#default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
#default CONFIG_USE_INIT=1
##
## Build code to setup a generic IOAPIC
##
@ -131,8 +162,10 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2735"
default MAINBOARD_PART_NUMBER="s2735"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2735
###
### LinuxBIOS layout values

20
src/mainboard/tyan/s2735/auto.c
View File

@ -10,7 +10,9 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
@ -51,6 +53,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#include "northbridge/intel/e7501/raminit.c"
#include "northbridge/intel/e7501/reset_test.c"
#include "sdram/generic_sdram.c"
@ -87,7 +90,7 @@ static void main(unsigned long bist)
#endif
if(!bios_reset_detected()) {
enable_smbus();
#if 1
#if 0
dump_spd_registers(&memctrl[0]);
// dump_smbus_registers();
#endif
@ -126,17 +129,16 @@ static void main(unsigned long bist)
print_debug_hex32(msr.lo);
print_debug("\r\n");
#endif
/*
#if 0
#if 0
ram_check(0x00000000, msr.lo+(msr.hi<<32));
#else
#if 1
#endif
#if 0
// Check 16MB of memory @ 0
ram_check(0x00000000, 0x01000000);
#else
// Check 16MB of memory @ 2GB
ram_check(0x80000000, 0x81000000);
// ram_check(0x80000000, 0x81000000);
#endif
#endif
*/
}

343
src/mainboard/tyan/s2735/cache_as_ram_auto.c Normal file
View File

@ -0,0 +1,343 @@
#define ASSEMBLY 1
#define __ROMCC__
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/intel/e7501/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
/* full reset */
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
#if 1
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
#endif
}
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/intel/e7501/raminit.c"
#include "northbridge/intel/e7501/reset_test.c"
#include "sdram/generic_sdram.c"
#include "cpu/intel/car/copy_and_run.c"
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/intel/i82801er/cmos_failover.c"
void real_main(unsigned long bist);
void amd64_main(unsigned long bist)
{
#if 1
#if 0
unsigned cmos_result;
int i;
for(i=0;i<2;i++) {
cmos_result = cmos_read(0x10);
outb(cmos_result, 0x80);
}
#endif
__asm__ volatile (
"movl $(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-4), %esi\n\t"
// "movl $(DCACHE_RAM_SIZE>>2), %ecx\n\t"
"movl $8, %ecx\n\t"
".yin1x:\n\t"
"movl %esi, %eax\n\t"
"movl $0x2000, %edx\n\t"
"movb %ah, %al\n\t"
".testy1:\n\t"
"outb %al, $0x80\n\t"
"decl %edx\n\t"
"jnz .testy1\n\t"
"movl (%esi), %eax\n\t"
"cmpb 0xff, %al\n\t"
"je .yin2\n\t"
"movl $0x2000, %edx\n\t"
".testy2:\n\t"
"outb %al, $0x80\n\t"
"decl %edx\n\t"
"jnz .testy2\n\t"
".yin2: decl %ecx\n\t"
"je .yout1x\n\t"
"sub $4, %esi\n\t"
"jmp .yin1x\n\t"
".yout1x:\n\t"
);
#endif
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else {
check_cmos_failed();
if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
cpu_reset:
// post_code(0x24);
#if 0
//CPU reset will reset memtroller ???
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
);
#endif
fallback_image:
// post_code(0x25);
real_main(bist);
}
void real_main(unsigned long bist)
#else
void amd64_main(unsigned long bist)
#endif
{
static const struct mem_controller memctrl[] = {
{
.d0 = PCI_DEV(0, 0, 0),
.d0f1 = PCI_DEV(0, 0, 1),
.channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
.channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
},
};
unsigned cpu_reset = 0;
#if 1
__asm__ volatile (
"movl $(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-4), %esi\n\t"
// "movl $(DCACHE_RAM_SIZE>>2), %ecx\n\t"
"movl $8, %ecx\n\t"
".zin1x:\n\t"
"movl %esi, %eax\n\t"
"movl $0x2000, %edx\n\t"
"movb %ah, %al\n\t"
".testz1:\n\t"
"outb %al, $0x80\n\t"
"decl %edx\n\t"
"jnz .testz1\n\t"
"movl (%esi), %eax\n\t"
"cmpb 0xff, %al\n\t"
"je .zin2\n\t"
"movl $0x2000, %edx\n\t"
".testz2:\n\t"
"outb %al, $0x80\n\t"
"decl %edx\n\t"
"jnz .testz2\n\t"
".zin2: decl %ecx\n\t"
"je .zout1x\n\t"
"sub $4, %esi\n\t"
"jmp .zin1x\n\t"
".zout1x:\n\t"
);
#endif
if (bist == 0)
{
// early_mtrr_init();
enable_lapic();
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
// setup_s2735_resource_map();
if(bios_reset_detected()) {
cpu_reset = 1;
goto cpu_reset_x;
}
enable_smbus();
#if 0
dump_spd_registers(&memctrl[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(1, memctrl);
#if 0
dump_pci_devices();
#endif
#if 1
dump_pci_device(PCI_DEV(0, 0, 0));
#endif
#if 1
{
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
#if CONFIG_USE_INIT
printk_debug("v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
#endif
}
#endif
#if 1
cpu_reset_x:
#if CONFIG_USE_INIT
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
#else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
#endif
if(cpu_reset == 0) {
print_debug("Clearing initial memory region: ");
}
print_debug("No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
"movl %0, %%ebx\n\t"
::"a" (cpu_reset)
);
if(cpu_reset==0) {
#define CLEAR_FIRST_1M_RAM 1
#include "cpu/intel/car/cache_as_ram_post.c"
}
else {
#undef CLEAR_FIRST_1M_RAM
#include "cpu/intel/car/cache_as_ram_post.c"
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"movl %0, %%ebp\n\t"
"movl %0, %%esp\n\t"
::"a"( _RAMBASE - 4 )
);
{
unsigned new_cpu_reset;
/* get back cpu_reset from ebx */
__asm__ volatile (
"movl %%ebx, %0\n\t"
:"=a" (new_cpu_reset)
);
/* We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) {
print_debug("Use Ram as Stack now - done\r\n");
} else
{
print_debug("Use Ram as Stack now - \r\n");
}
#if CONFIG_USE_INIT
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
/*copy and execute linuxbios_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
#endif
print_debug("should not be here -\r\n");
}

6
src/mainboard/tyan/s2850/Options.lb
View File

@ -57,6 +57,8 @@ uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_E0_MEM_HOLE_SIZEK
uses CONFIG_USE_INIT
###
### Build options
###
@ -139,8 +141,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2850"
default MAINBOARD_PART_NUMBER="s2850"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2850

10
src/mainboard/tyan/s2875/Options.lb
View File

@ -56,6 +56,8 @@ uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_E0_MEM_HOLE_SIZEK
uses CONFIG_USE_INIT
###
### Build options
###
@ -124,8 +126,8 @@ default CONFIG_LOGICAL_CPUS=0
default K8_E0_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
#default CONFIG_CONSOLE_VGA=1
#default CONFIG_PCI_ROM_RUN=1
##
## Build code to setup a generic IOAPIC
@ -135,8 +137,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2875"
default MAINBOARD_PART_NUMBER="s2875"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2875

6
src/mainboard/tyan/s2880/Options.lb
View File

@ -56,6 +56,8 @@ uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_E0_MEM_HOLE_SIZEK
uses CONFIG_USE_INIT
###
### Build options
###
@ -135,8 +137,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2880"
default MAINBOARD_PART_NUMBER="s2880"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880

69
src/mainboard/tyan/s2881/Config.lb
View File

@ -39,10 +39,33 @@ arch i386 end
##
driver mainboard.o
#dir /drivers/si/3114
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
@ -66,13 +89,22 @@ makerule ./auto.inc
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
@ -85,8 +117,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
@ -94,20 +129,44 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
##
## Setup RAM
##
@ -118,11 +177,13 @@ mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
config chip.h
end
# sample config for tyan/s2881

22
src/mainboard/tyan/s2881/Options.lb
View File

@ -47,6 +47,7 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
@ -56,6 +57,11 @@ uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_E0_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
###
### Build options
###
@ -120,6 +126,9 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_E0_MEM_HOLE_SIZEK=0x100000
@ -127,6 +136,15 @@ default K8_E0_MEM_HOLE_SIZEK=0x100000
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
##
## Build code to setup a generic IOAPIC
##
@ -135,8 +153,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2881"
default MAINBOARD_PART_NUMBER="s2881"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881

393
src/mainboard/tyan/s2881/cache_as_ram_auto.c Normal file
View File

@ -0,0 +1,393 @@
#define ASSEMBLY 1
#define __ROMCC__
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#define K8_HT_FREQ_1G_SUPPORT 0
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
#include "cpu/amd/car/copy_and_run.c"
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void real_main(unsigned long bist);
void amd64_main(unsigned long bist)
{
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Make cerain my local apic is useable */
// enable_lapic();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
/* Is this a cpu only reset? */
if (cpu_init_detected(id.nodeid)) {
#else
// nodeid = lapicid();
nodeid = get_node_id();
/* Is this a cpu only reset? */
if (cpu_init_detected(nodeid)) {
#endif
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
// post_code(0x21);
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the ck804 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
cpu_reset:
// post_code(0x24);
#if 0
//CPU reset will reset memtroller ???
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
);
#endif
fallback_image:
// post_code(0x25);
real_main(bist);
}
void real_main(unsigned long bist)
#else
void amd64_main(unsigned long bist)
#endif
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
},
#endif
#if SECOND_CPU
{
.node_id = 1,
.f0 = PCI_DEV(0, 0x19, 0),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
#endif
};
int needs_reset;
unsigned cpu_reset = 0;
if (bist == 0) {
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Skip this if there was a built in self test failure */
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#else
nodeid = get_node_id();
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(id.nodeid);
}
#else
if (cpu_init_detected(nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
// We need stop the CACHE as RAM for this CPU too
#include "cpu/amd/car/cache_as_ram_post.c"
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s2881_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();
#endif
#if 1
{
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
#if CONFIG_USE_INIT
printk_debug("v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
#endif
}
#endif
cpu_reset_x:
#if CONFIG_USE_INIT
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
#else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
#endif
if(cpu_reset == 0) {
print_debug("Clearing initial memory region: ");
}
print_debug("No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
"movl %0, %%ebx\n\t"
::"a" (cpu_reset)
);
if(cpu_reset==0) {
#define CLEAR_FIRST_1M_RAM 1
#include "cpu/amd/car/cache_as_ram_post.c"
}
else {
#undef CLEAR_FIRST_1M_RAM
#include "cpu/amd/car/cache_as_ram_post.c"
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"movl %0, %%ebp\n\t"
"movl %0, %%esp\n\t"
::"a"( _RAMBASE - 4 )
);
{
unsigned new_cpu_reset;
/* get back cpu_reset from ebx */
__asm__ volatile (
"movl %%ebx, %0\n\t"
:"=a" (new_cpu_reset)
);
print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) {
print_debug("done\r\n");
} else
{
print_debug("\r\n");
}
#if CONFIG_USE_INIT
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
/*copy and execute linuxbios_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
print_debug("should not be here -\r\n");
}

70
src/mainboard/tyan/s2882/Config.lb
View File

@ -39,10 +39,34 @@ arch i386 end
##
driver mainboard.o
#dir /drivers/si/3114
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
##
@ -65,13 +89,22 @@ makerule ./auto.inc
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
@ -84,8 +117,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
@ -93,20 +129,44 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
##
## Setup RAM
##
@ -117,11 +177,13 @@ mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
config chip.h
end
# sample config for tyan/s2882

22
src/mainboard/tyan/s2882/Options.lb
View File

@ -47,6 +47,7 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
@ -56,6 +57,11 @@ uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_E0_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
###
### Build options
###
@ -120,6 +126,9 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_E0_MEM_HOLE_SIZEK=0x100000
@ -127,6 +136,15 @@ default K8_E0_MEM_HOLE_SIZEK=0x100000
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
##
## Build code to setup a generic IOAPIC
##
@ -135,8 +153,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2882"
default MAINBOARD_PART_NUMBER="s2882"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882

389
src/mainboard/tyan/s2882/cache_as_ram_auto.c Normal file
View File

@ -0,0 +1,389 @@
#define ASSEMBLY 1
#define __ROMCC__
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#define K8_HT_FREQ_1G_SUPPORT 0
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
#include "cpu/amd/car/copy_and_run.c"
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void real_main(unsigned long bist);
void amd64_main(unsigned long bist)
{
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Make cerain my local apic is useable */
// enable_lapic();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
/* Is this a cpu only reset? */
if (cpu_init_detected(id.nodeid)) {
#else
// nodeid = lapicid();
nodeid = get_node_id();
/* Is this a cpu only reset? */
if (cpu_init_detected(nodeid)) {
#endif
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the ck804 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
cpu_reset:
#if 0
//CPU reset will reset memtroller ???
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
);
#endif
fallback_image:
real_main(bist);
}
void real_main(unsigned long bist)
#else
void amd64_main(unsigned long bist)
#endif
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
},
#endif
#if SECOND_CPU
{
.node_id = 1,
.f0 = PCI_DEV(0, 0x19, 0),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
#endif
};
int needs_reset;
unsigned cpu_reset = 0;
if (bist == 0) {
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Skip this if there was a built in self test failure */
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#else
nodeid = get_node_id();
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(id.nodeid);
}
#else
if (cpu_init_detected(nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
// We need stop the CACHE as RAM for this CPU too
#include "cpu/amd/car/cache_as_ram_post.c"
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_default_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();
#endif
#if 1
{
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
#if CONFIG_USE_INIT
printk_debug("v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
#endif
}
#endif
cpu_reset_x:
#if CONFIG_USE_INIT
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
#else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
#endif
if(cpu_reset == 0) {
print_debug("Clearing initial memory region: ");
}
print_debug("No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
"movl %0, %%ebx\n\t"
::"a" (cpu_reset)
);
if(cpu_reset==0) {
#define CLEAR_FIRST_1M_RAM 1
#include "cpu/amd/car/cache_as_ram_post.c"
}
else {
#undef CLEAR_FIRST_1M_RAM
#include "cpu/amd/car/cache_as_ram_post.c"
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"movl %0, %%ebp\n\t"
"movl %0, %%esp\n\t"
::"a"( _RAMBASE - 4 )
);
{
unsigned new_cpu_reset;
/* get back cpu_reset from ebx */
__asm__ volatile (
"movl %%ebx, %0\n\t"
:"=a" (new_cpu_reset)
);
print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) {
print_debug("done\r\n");
} else
{
print_debug("\r\n");
}
#if CONFIG_USE_INIT
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
/*copy and execute linuxbios_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
print_debug("should not be here -\r\n");
}

64
src/mainboard/tyan/s2885/Config.lb
View File

@ -46,6 +46,26 @@ if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
@ -69,13 +89,22 @@ makerule ./auto.inc
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
@ -88,8 +117,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
@ -97,20 +129,44 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
##
## Setup RAM
##
@ -121,6 +177,8 @@ mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files
##

18
src/mainboard/tyan/s2885/Options.lb
View File

@ -57,6 +57,11 @@ uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_E0_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
###
### Build options
###
@ -131,6 +136,15 @@ default K8_E0_MEM_HOLE_SIZEK=0x100000
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
##
## Build code to setup a generic IOAPIC
##
@ -139,8 +153,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2885"
default MAINBOARD_PART_NUMBER="s2885"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2885

472
src/mainboard/tyan/s2885/cache_as_ram_auto.c Normal file
View File

@ -0,0 +1,472 @@
#define ASSEMBLY 1
#define __ROMCC__
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include "northbridge/amd/amdk8/cpu_rev.c"
#define K8_HT_FREQ_1G_SUPPORT 0
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#if 0
#define ENABLE_APIC_EXT_ID 1
#define APIC_ID_OFFSET 0x10
#define LIFT_BSP_APIC_ID 0
#else
#define ENABLE_APIC_EXT_ID 0
#endif
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
#include "cpu/amd/car/copy_and_run.c"
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void real_main(unsigned long bist);
void amd64_main(unsigned long bist)
{
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Make cerain my local apic is useable */
// enable_lapic();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
/* Is this a cpu only reset? */
if (cpu_init_detected(id.nodeid)) {
#else
// nodeid = lapicid();
nodeid = get_node_id();
/* Is this a cpu only reset? */
if (cpu_init_detected(nodeid)) {
#endif
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
// post_code(0x21);
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the ck804 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
// post_code(0x22);
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
// post_code(0x23);
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
cpu_reset:
// post_code(0x24);
#if 0
//CPU reset will reset memtroller ???
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
);
#endif
fallback_image:
// post_code(0x25);
real_main(bist);
}
void real_main(unsigned long bist)
#else
void amd64_main(unsigned long bist)
#endif
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
},
#endif
#if SECOND_CPU
{
.node_id = 1,
.f0 = PCI_DEV(0, 0x19, 0),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
#endif
};
int needs_reset;
unsigned cpu_reset = 0;
if (bist == 0) {
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Skip this if there was a built in self test failure */
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#if ENABLE_APIC_EXT_ID == 1
if(id.coreid == 0) {
enable_apic_ext_id(id.nodeid);
}
#endif
#else
nodeid = get_node_id();
#if ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(nodeid);
#endif
#endif
enable_lapic();
init_timer();
// post_code(0x30);
#if CONFIG_LOGICAL_CPUS==1
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if( id.nodeid != 0 ) //all except cores in node0
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
#endif
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
// __asm__ volatile ("jmp __cpu_reset");
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(id.nodeid);
// start_other_core(id.nodeid);
}
#else
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if(nodeid != 0)
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
#endif
if (cpu_init_detected(nodeid)) {
// __asm__ volatile ("jmp __cpu_reset");
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(nodeid);
#endif
// post_code(0x31);
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
// We need stop the CACHE as RAM for this CPU too
#include "cpu/amd/car/cache_as_ram_post.c"
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s2885_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
#if 0
// You need to preset bus num in PCI_DEV(0, 0x18,1) 0xe0, 0xe4, 0xe8, 0xec
needs_reset |= ht_setup_chains(2);
#else
// automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();
#endif
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();
#endif
/* Check all of memory */
#if 0
msr_t msr;
msr = rdmsr(TOP_MEM2);
print_debug("TOP_MEM2: ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\r\n");
#endif
#if 0
ram_check(0x00000000, msr.lo+(msr.hi<<32));
#endif
#if 0
// Check 16MB of memory @ 0
ram_check(0x00000000, 0x00100000);
// Check 16MB of memory @ 2GB
ram_check(0x80000000, 0x80100000);
#endif
#if 1
{
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
#if CONFIG_USE_INIT
printk_debug("v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
#endif
}
#endif
#if 1
cpu_reset_x:
#if CONFIG_USE_INIT
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
#else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
#endif
if(cpu_reset == 0) {
print_debug("Clearing initial memory region: ");
}
print_debug("No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
"movl %0, %%ebx\n\t"
::"a" (cpu_reset)
);
if(cpu_reset==0) {
#define CLEAR_FIRST_1M_RAM 1
#include "cpu/amd/car/cache_as_ram_post.c"
}
else {
#undef CLEAR_FIRST_1M_RAM
#include "cpu/amd/car/cache_as_ram_post.c"
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"movl %0, %%ebp\n\t"
"movl %0, %%esp\n\t"
::"a"( _RAMBASE - 4 )
);
{
unsigned new_cpu_reset;
/* get back cpu_reset from ebx */
__asm__ volatile (
"movl %%ebx, %0\n\t"
:"=a" (new_cpu_reset)
);
print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) {
print_debug("done\r\n");
} else
{
print_debug("\r\n");
}
#if CONFIG_USE_INIT
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
/*copy and execute linuxbios_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
#endif
print_debug("should not be here -\r\n");
}

140
src/mainboard/tyan/s2891/Config.lb
View File

@ -47,26 +47,51 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -75,7 +100,16 @@ end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
@ -88,8 +122,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
@ -105,14 +142,24 @@ if USE_FALLBACK_IMAGE
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
ldscript /arch/i386/lib/failover.lds
if USE_DCACHE_RAM
else
mainboardinit ./failover.inc
end
end
###
@ -122,12 +169,25 @@ end
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
# ROMCC
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files
@ -247,7 +307,8 @@ chip northbridge/amd/amdk8/root_complex
# chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 7.0 on end
register "rom_address" = "0xfff80000"
register "rom_address" = "0xfff80000" #for 512K
#register "rom_address" = "0xfff00000" #for 1M
end
end
device pci a.0 off end # NIC
@ -283,13 +344,14 @@ chip northbridge/amd/amdk8/root_complex
end #mc0
end # pci_domain
# chip drivers/generic/debug
# device pnp 0.0 off end
# device pnp 0.1 off end
# device pnp 0.2 off end
# device pnp 0.3 off end
# device pnp 0.4 off end
# device pnp 0.5 on end
# end
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# end
end # root_complex

32
src/mainboard/tyan/s2891/Options.lb
View File

@ -60,10 +60,19 @@ uses K8_E0_MEM_HOLE_SIZEK
uses CK804_DEVN_BASE
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
default ROM_SIZE=524288
#1M bytes
#default ROM_SIZE=1048576
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
@ -83,9 +92,9 @@ default HAVE_FALLBACK_BOOT=1
##
default HAVE_HARD_RESET=1
default HARD_RESET_BUS=1
default HARD_RESET_DEVICE=4
default HARD_RESET_FUNCTION=0
#default HARD_RESET_BUS=1
#default HARD_RESET_DEVICE=4
#default HARD_RESET_FUNCTION=0
##
## Build code to export a programmable irq routing table
@ -131,8 +140,17 @@ default CK804_DEVN_BASE=0
#default CONFIG_CONSOLE_BTEXT=1
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
#default CONFIG_CONSOLE_VGA=1
#default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
##
## Build code to setup a generic IOAPIC
@ -142,8 +160,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2891"
default MAINBOARD_PART_NUMBER="s2891"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891

411
src/mainboard/tyan/s2891/cache_as_ram_auto.c Normal file
View File

@ -0,0 +1,411 @@
#define ASSEMBLY 1
#define __ROMCC__
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
//#define K8_HT_FREQ_1G_SUPPORT 1
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* full reset */
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
#if 1
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
#endif
}
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
#define CK804_NUM 1
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
#include "cpu/amd/car/copy_and_run.c"
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<0) | (1<<1);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
#if 1
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
#endif
}
void real_main(unsigned long bist);
void amd64_main(unsigned long bist)
{
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Make cerain my local apic is useable */
// enable_lapic();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
/* Is this a cpu only reset? */
if (cpu_init_detected(id.nodeid)) {
#else
// nodeid = lapicid() & 0xf;
nodeid = get_node_id();
/* Is this a cpu only reset? */
if (cpu_init_detected(nodeid)) {
#endif
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
cpu_reset:
#if 0
//CPU reset will reset memtroller ???
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
);
#endif
fallback_image:
real_main(bist);
}
void real_main(unsigned long bist)
#else
void amd64_main(unsigned long bist)
#endif
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
},
#endif
#if SECOND_CPU
{
.node_id = 1,
.f0 = PCI_DEV(0, 0x19, 0),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
#endif
};
int needs_reset;
unsigned cpu_reset = 0;
if (bist == 0) {
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Skip this if there was a built in self test failure */
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#else
nodeid = get_node_id();
#endif
enable_lapic();
// init_timer();
#if CONFIG_LOGICAL_CPUS==1
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(id.nodeid);
}
#else
if (cpu_init_detected(nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
// We need stop the CACHE as RAM for this CPU too
#include "cpu/amd/car/cache_as_ram_post.c"
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
init_timer(); // only do it it first CPU
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s2891_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();
#endif
#if 1
{
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
#if CONFIG_USE_INIT
printk_debug("v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
#endif
}
#endif
cpu_reset_x:
#if CONFIG_USE_INIT
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
#else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
#endif
if(cpu_reset == 0) {
print_debug("Clearing initial memory region: ");
}
print_debug("No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
"movl %0, %%ebx\n\t"
::"a" (cpu_reset)
);
if(cpu_reset==0) {
#define CLEAR_FIRST_1M_RAM 1
#include "cpu/amd/car/cache_as_ram_post.c"
}
else {
#undef CLEAR_FIRST_1M_RAM
#include "cpu/amd/car/cache_as_ram_post.c"
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"movl %0, %%ebp\n\t"
"movl %0, %%esp\n\t"
::"a"( _RAMBASE - 4 )
);
{
unsigned new_cpu_reset;
/* get back cpu_reset from ebx */
__asm__ volatile (
"movl %%ebx, %0\n\t"
:"=a" (new_cpu_reset)
);
/* We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) {
print_debug("Use Ram as Stack now - done\r\n");
} else
{
print_debug("Use Ram as Stack now - \r\n");
}
#if CONFIG_USE_INIT
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
/*copy and execute linuxbios_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
print_debug("should not be here -\r\n");
}

64
src/mainboard/tyan/s2892/Config.lb
View File

@ -47,6 +47,28 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
##
@ -69,13 +91,25 @@ makerule ./auto.inc
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
@ -88,8 +122,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
@ -105,15 +142,26 @@ if USE_FALLBACK_IMAGE
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
@ -122,6 +170,16 @@ end
##
## Setup RAM
##
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
# ROMCC
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
@ -129,6 +187,8 @@ mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files
##

27
src/mainboard/tyan/s2892/Options.lb
View File

@ -60,10 +60,19 @@ uses K8_E0_MEM_HOLE_SIZEK
uses CK804_DEVN_BASE
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
default ROM_SIZE=524288
#1M bytes
#default ROM_SIZE=1048576
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
@ -83,9 +92,9 @@ default HAVE_FALLBACK_BOOT=1
##
default HAVE_HARD_RESET=1
default HARD_RESET_BUS=1
default HARD_RESET_DEVICE=4
default HARD_RESET_FUNCTION=0
#default HARD_RESET_BUS=1
#default HARD_RESET_DEVICE=4
#default HARD_RESET_FUNCTION=0
##
## Build code to export a programmable irq routing table
@ -134,6 +143,14 @@ default CK804_DEVN_BASE=0
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
##
## Build code to setup a generic IOAPIC
@ -143,8 +160,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2892"
default MAINBOARD_PART_NUMBER="s2892"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892

415
src/mainboard/tyan/s2892/cache_as_ram_auto.c Normal file
View File

@ -0,0 +1,415 @@
#define ASSEMBLY 1
#define __ROMCC__
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#define K8_HT_FREQ_1G_SUPPORT 0
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* full reset */
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
#if 1
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
#endif
}
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
#define CK804_NUM 1
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
#define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
#include "cpu/amd/car/copy_and_run.c"
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<0);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
}
void real_main(unsigned long bist);
void amd64_main(unsigned long bist)
{
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Make cerain my local apic is useable */
// enable_lapic();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
/* Is this a cpu only reset? */
if (cpu_init_detected(id.nodeid)) {
#else
// nodeid = lapicid() & 0xf;
nodeid = get_node_id();
/* Is this a cpu only reset? */
if (cpu_init_detected(nodeid)) {
#endif
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
cpu_reset:
#if 0
//CPU reset will reset memtroller ???
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
);
#endif
fallback_image:
real_main(bist);
}
void real_main(unsigned long bist)
#else
void amd64_main(unsigned long bist)
#endif
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
},
#endif
#if SECOND_CPU
{
.node_id = 1,
.f0 = PCI_DEV(0, 0x19, 0),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
#endif
};
int needs_reset;
unsigned cpu_reset = 0;
if (bist == 0) {
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Skip this if there was a built in self test failure */
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#else
nodeid = get_node_id();
#endif
enable_lapic();
// init_timer();
#if CONFIG_LOGICAL_CPUS==1
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(id.nodeid);
}
#else
if (cpu_init_detected(nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
// We need stop the CACHE as RAM for this CPU too
#include "cpu/amd/car/cache_as_ram_post.c"
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
init_timer(); // only do it it first CPU
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s2892_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();
#endif
#if 1
{
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
#if CONFIG_USE_INIT
printk_debug("v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
#endif
}
#endif
cpu_reset_x:
#if CONFIG_USE_INIT
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
#else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
#endif
if(cpu_reset == 0) {
print_debug("Clearing initial memory region: ");
}
print_debug("No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
"movl %0, %%ebx\n\t"
::"a" (cpu_reset)
);
if(cpu_reset==0) {
#define CLEAR_FIRST_1M_RAM 1
#include "cpu/amd/car/cache_as_ram_post.c"
}
else {
#undef CLEAR_FIRST_1M_RAM
#include "cpu/amd/car/cache_as_ram_post.c"
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"movl %0, %%ebp\n\t"
"movl %0, %%esp\n\t"
::"a"( _RAMBASE - 4 )
);
{
unsigned new_cpu_reset;
/* get back cpu_reset from ebx */
__asm__ volatile (
"movl %%ebx, %0\n\t"
:"=a" (new_cpu_reset)
);
/* We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) {
print_debug("Use Ram as Stack now - done\r\n");
} else
{
print_debug("Use Ram as Stack now - \r\n");
}
#if CONFIG_USE_INIT
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
/*copy and execute linuxbios_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
print_debug("should not be here -\r\n");
}

117
src/mainboard/tyan/s2895/Config.lb
View File

@ -44,27 +44,46 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if USE_DCACHE_RAM
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
else
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
@ -73,7 +92,16 @@ end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
@ -86,8 +114,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
@ -103,29 +134,49 @@ if USE_FALLBACK_IMAGE
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
ldscript /arch/i386/lib/failover.lds
if USE_DCACHE_RAM
else
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
# ROMCC
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
## Include the secondary Configuration files

25
src/mainboard/tyan/s2895/Options.lb
View File

@ -59,6 +59,11 @@ uses K8_E0_MEM_HOLE_SIZEK
uses CK804_DEVN_BASE
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes
default ROM_SIZE=524288
@ -85,9 +90,9 @@ default HAVE_FALLBACK_BOOT=1
##
default HAVE_HARD_RESET=1
default HARD_RESET_BUS=1
default HARD_RESET_DEVICE=4
default HARD_RESET_FUNCTION=0
#default HARD_RESET_BUS=1
#default HARD_RESET_DEVICE=4
#default HARD_RESET_FUNCTION=0
##
## Build code to export a programmable irq routing table
@ -135,6 +140,14 @@ default CK804_DEVN_BASE=0
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
##
## Build code to setup a generic IOAPIC
##
@ -143,8 +156,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s2895"
default MAINBOARD_PART_NUMBER="s2895"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
@ -233,7 +246,7 @@ default TTYS0_LCS=0x3
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=7
default DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8

492
src/mainboard/tyan/s2895/cache_as_ram_auto.c Normal file
View File

@ -0,0 +1,492 @@
#define ASSEMBLY 1
#define __ROMCC__
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#define K8_HT_FREQ_1G_SUPPORT 0
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* full reset */
outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
#if 1
/* link reset */
outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9);
#endif
}
static void memreset_setup(void)
{
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
static void sio_gpio_setup(void){
unsigned value;
#if 1
/*Enable onboard scsi*/
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
#endif
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#if 0
#define ENABLE_APIC_EXT_ID 1
#define APIC_ID_OFFSET 0x10
#define LIFT_BSP_APIC_ID 0
#else
#define ENABLE_APIC_EXT_ID 0
#endif
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
#define CK804_NUM 2
//#define CK804B_BUSN 0x80
#define CK804B_BUSN 0xc
#define CK804_USE_NIC 1
#define CK804_USE_ACI 1
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
#define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
#include "cpu/amd/car/copy_and_run.c"
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
{
unsigned value;
uint32_t dword;
uint8_t byte;
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<29)|(1<<0);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
#if 1
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
value &= 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
#endif
}
void real_main(unsigned long bist);
void amd64_main(unsigned long bist)
{
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Make cerain my local apic is useable */
// enable_lapic();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
/* Is this a cpu only reset? */
if (cpu_init_detected(id.nodeid)) {
#else
// nodeid = lapicid() & 0xf;
nodeid = get_node_id();
/* Is this a cpu only reset? */
if (cpu_init_detected(nodeid)) {
#endif
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the ck804 */
ck804_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
cpu_reset:
#if 0
//CPU reset will reset memtroller ???
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
);
#endif
fallback_image:
real_main(bist);
}
void real_main(unsigned long bist)
#else
void amd64_main(unsigned long bist)
#endif
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
},
#endif
#if SECOND_CPU
{
.node_id = 1,
.f0 = PCI_DEV(0, 0x19, 0),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
},
#endif
};
int needs_reset;
unsigned cpu_reset = 0;
if (bist == 0) {
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Skip this if there was a built in self test failure */
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#if ENABLE_APIC_EXT_ID == 1
if(id.coreid == 0) {
enable_apic_ext_id(id.nodeid);
}
#endif
#else
nodeid = get_node_id();
#if ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(nodeid);
#endif
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if( id.nodeid != 0 ) //all except cores in node0
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
#endif
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(id.nodeid);
}
#else
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if(nodeid != 0)
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
#endif
if (cpu_init_detected(nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
// We need stop the CACHE as RAM for this CPU too
#include "cpu/amd/car/cache_as_ram_post.c"
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s2895_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
#if CK804B_BUSN == 0x80
// You need to preset bus num in PCI_DEV(0, 0x18,1) 0xe0, 0xe4, 0xe8, 0xec
needs_reset |= ht_setup_chains(3);
#else
// automatically set that for you, but you might meet tight space
// Bcause it has two Ck804, we need to set CK804B_BUSN to 0xc (ht_setup_chains_x will let second CK804 use that bus num.
// otherwise ck804_eary_setup can not work rightly.
needs_reset |= ht_setup_chains_x();
#endif
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
#endif
#if 0
dump_smbus_registers();
#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 0
dump_pci_devices();
#endif
#if 1
{
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
#if CONFIG_USE_INIT
printk_debug("v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
#endif
}
#endif
cpu_reset_x:
#if CONFIG_USE_INIT
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
#else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
#endif
if(cpu_reset == 0) {
print_debug("Clearing initial memory region: ");
}
print_debug("No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
"movl %0, %%ebx\n\t"
::"a" (cpu_reset)
);
if(cpu_reset==0) {
#define CLEAR_FIRST_1M_RAM 1
#include "cpu/amd/car/cache_as_ram_post.c"
}
else {
#undef CLEAR_FIRST_1M_RAM
#include "cpu/amd/car/cache_as_ram_post.c"
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"movl %0, %%ebp\n\t"
"movl %0, %%esp\n\t"
::"a"( _RAMBASE - 4 )
);
{
unsigned new_cpu_reset;
/* get back cpu_reset from ebx */
__asm__ volatile (
"movl %%ebx, %0\n\t"
:"=a" (new_cpu_reset)
);
/* We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) {
print_debug("Use Ram as Stack now - done\r\n");
} else
{
print_debug("Use Ram as Stack now - \r\n");
}
#if CONFIG_USE_INIT
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
/*copy and execute linuxbios_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
print_err("should not be here -\r\n");
}

10
src/mainboard/tyan/s4880/Options.lb
View File

@ -11,6 +11,7 @@ uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses SERIAL_CPU_INIT
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
@ -56,6 +57,8 @@ uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_E0_MEM_HOLE_SIZEK
uses CONFIG_USE_INIT
###
### Build options
###
@ -120,6 +123,9 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=4
default CONFIG_LOGICAL_CPUS=0
#default SERIAL_CPU_INIT=0
#1G memory hole
default K8_E0_MEM_HOLE_SIZEK=0x100000
@ -135,8 +141,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s4880"
default MAINBOARD_PART_NUMBER="s4880"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880

138
src/mainboard/tyan/s4882/Config.lb
View File

@ -16,6 +16,7 @@ end
##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
@ -34,6 +35,7 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end
##
## Build the objects we have code for in this directory.
##
@ -42,39 +44,61 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if USE_DCACHE_RAM
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
if CONFIG_USE_INIT
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
else
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
mainboardinit arch/i386/lib/jmp_auto_out.inc
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ./romcc"
action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##
## Setup RAM
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
mainboardinit arch/i386/lib/jmp_auto_out.inc
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
@ -82,7 +106,16 @@ mainboardinit arch/i386/lib/jmp_auto_out.inc
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
## Build our reset vector (This is where linuxBIOS is entered)
@ -95,8 +128,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
if USE_DCACHE_RAM
else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
end
##
## Include an id string (For safe flashing)
@ -104,27 +140,51 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
else
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if USE_DCACHE_RAM
mainboardinit arch/i386/lib/jmp_auto.inc
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
else
# ROMCC
mainboardinit arch/i386/lib/jmp_auto.inc
end
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
config chip.h
config chip.h
end
# sample config for tyan/s4882

33
src/mainboard/tyan/s4882/Options.lb
View File

@ -11,7 +11,6 @@ uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses SERIAL_CPU_INIT
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
@ -48,16 +47,21 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_BTEXT
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_E0_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
###
### Build options
###
@ -85,7 +89,7 @@ default HAVE_HARD_RESET=1
##
## Funky hard reset implementation
##
default HARD_RESET_BUS=1
default HARD_RESET_BUS=3
default HARD_RESET_DEVICE=4
default HARD_RESET_FUNCTION=0
@ -122,18 +126,25 @@ default CONFIG_MAX_CPUS=8
default CONFIG_MAX_PHYSICAL_CPUS=4
default CONFIG_LOGICAL_CPUS=1
#default SERIAL_CPU_INIT=0
#CHIP_NAME ?
default CONFIG_CHIP_NAME=1
#1G memory hole
default K8_E0_MEM_HOLE_SIZEK=0x100000
#BTEXT Console
#default CONFIG_CONSOLE_BTEXT=1
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=1
##
## Build code to setup a generic IOAPIC
##
@ -142,8 +153,8 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default MAINBOARD_PART_NUMBER="Tyan"
default MAINBOARD_VENDOR="s4882"
default MAINBOARD_PART_NUMBER="s4882"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4882
@ -232,9 +243,9 @@ default TTYS0_LCS=0x3
## SPEW 9 Way too many details
## Request this level of debugging output
default DEFAULT_CONSOLE_LOGLEVEL=7
default DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=7
default MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting

457
src/mainboard/tyan/s4882/cache_as_ram_auto.c Normal file
View File

@ -0,0 +1,457 @@
#define ASSEMBLY 1
#define __ROMCC__
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#define K8_HT_FREQ_1G_SUPPORT 0
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void hard_reset(void)
{
set_bios_reset();
/* enable cf9 */
pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
set_bios_reset();
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
}
else {
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
}
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
int ret,i;
unsigned device=(ctrl->channel0[0])>>8;
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
} while ((ret!=0) && (i-->0));
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#if 0
#define ENABLE_APIC_EXT_ID 1
#define APIC_ID_OFFSET 0x10
#define LIFT_BSP_APIC_ID 0
#else
#define ENABLE_APIC_EXT_ID 0
#endif
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
/* tyan does not want the default */
#include "resourcemap.c"
#if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1
#include "cpu/amd/dualcore/dualcore.c"
#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
#define THIRD_CPU 1
#define FOURTH_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
#define RC0 ((1<<2)<<8)
#define RC1 ((1<<1)<<8)
#define RC2 ((1<<4)<<8)
#define RC3 ((1<<3)<<8)
#define DIMM0 0x50
#define DIMM1 0x51
#define DIMM2 0x52
#define DIMM3 0x53
#include "cpu/amd/car/copy_and_run.c"
#if USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void real_main(unsigned long bist);
void amd64_main(unsigned long bist)
{
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Make cerain my local apic is useable */
// enable_lapic();
#if CONFIG_LOGICAL_CPUS==1
id = get_node_core_id_x();
/* Is this a cpu only reset? */
if (cpu_init_detected(id.nodeid)) {
#else
// nodeid = lapicid();
nodeid = get_node_id();
/* Is this a cpu only reset? */
if (cpu_init_detected(nodeid)) {
#endif
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the ck804 */
amd8111_enable_rom();
/* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
__asm__ volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
);
cpu_reset:
#if 0
//CPU reset will reset memtroller ???
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
);
#endif
fallback_image:
real_main(bist);
}
void real_main(unsigned long bist)
#else
void amd64_main(unsigned long bist)
#endif
{
static const struct mem_controller cpu[] = {
#if FIRST_CPU
{
.node_id = 0,
.f0 = PCI_DEV(0, 0x18, 0),
.f1 = PCI_DEV(0, 0x18, 1),
.f2 = PCI_DEV(0, 0x18, 2),
.f3 = PCI_DEV(0, 0x18, 3),
.channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
.channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
},
#endif
#if SECOND_CPU
{
.node_id = 1,
.f0 = PCI_DEV(0, 0x19, 0),
.f1 = PCI_DEV(0, 0x19, 1),
.f2 = PCI_DEV(0, 0x19, 2),
.f3 = PCI_DEV(0, 0x19, 3),
.channel0 = { RC1|DIMM0, RC1|DIMM2 , 0, 0 },
.channel1 = { RC1|DIMM1, RC1|DIMM3 , 0, 0 },
},
#endif
#if THIRD_CPU
{
.node_id = 2,
.f0 = PCI_DEV(0, 0x1a, 0),
.f1 = PCI_DEV(0, 0x1a, 1),
.f2 = PCI_DEV(0, 0x1a, 2),
.f3 = PCI_DEV(0, 0x1a, 3),
.channel0 = { RC2|DIMM0, RC2|DIMM2, 0, 0 },
.channel1 = { RC2|DIMM1, RC2|DIMM3, 0, 0 },
},
#endif
#if FOURTH_CPU
{
.node_id = 3,
.f0 = PCI_DEV(0, 0x1b, 0),
.f1 = PCI_DEV(0, 0x1b, 1),
.f2 = PCI_DEV(0, 0x1b, 2),
.f3 = PCI_DEV(0, 0x1b, 3),
.channel0 = { RC3|DIMM0, RC3|DIMM2, 0, 0 },
.channel1 = { RC3|DIMM1, RC3|DIMM3, 0, 0 },
},
#endif
};
int needs_reset;
unsigned cpu_reset = 0;
if (bist == 0) {
#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
#else
unsigned nodeid;
#endif
/* Skip this if there was a built in self test failure */
// amd_early_mtrr_init(); # don't need, already done in cache_as_ram
#if CONFIG_LOGICAL_CPUS==1
set_apicid_cpuid_lo();
id = get_node_core_id_x(); // that is initid
#if ENABLE_APIC_EXT_ID == 1
if(id.coreid == 0) {
enable_apic_ext_id(id.nodeid);
}
#endif
#else
nodeid = get_node_id();
#if ENABLE_APIC_EXT_ID == 1
enable_apic_ext_id(nodeid);
#endif
#endif
enable_lapic();
init_timer();
#if CONFIG_LOGICAL_CPUS==1
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if( id.nodeid != 0 ) //all except cores in node0
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
#endif
if(id.coreid == 0) {
if (cpu_init_detected(id.nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(id.nodeid);
}
#else
#if ENABLE_APIC_EXT_ID == 1
#if LIFT_BSP_APIC_ID == 0
if(nodeid != 0)
#endif
lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
#endif
if (cpu_init_detected(nodeid)) {
cpu_reset = 1;
goto cpu_reset_x;
}
distinguish_cpu_resets(nodeid);
#endif
if (!boot_cpu()
#if CONFIG_LOGICAL_CPUS==1
|| (id.coreid != 0)
#endif
) {
// We need stop the CACHE as RAM for this CPU too
#include "cpu/amd/car/cache_as_ram_post.c"
stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
setup_s4882_resource_map();
#if 0
dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
enable_smbus();
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 1
{
/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
unsigned v_esp;
__asm__ volatile (
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
#if CONFIG_USE_INIT
printk_debug("v_esp=%08x\r\n", v_esp);
#else
print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
#endif
}
#endif
cpu_reset_x:
#if CONFIG_USE_INIT
printk_debug("cpu_reset = %08x\r\n",cpu_reset);
#else
print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
#endif
if(cpu_reset == 0) {
print_debug("Clearing initial memory region: ");
}
print_debug("No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
"movl %0, %%ebx\n\t"
::"a" (cpu_reset)
);
if(cpu_reset==0) {
#define CLEAR_FIRST_1M_RAM 1
#include "cpu/amd/car/cache_as_ram_post.c"
}
else {
#undef CLEAR_FIRST_1M_RAM
#include "cpu/amd/car/cache_as_ram_post.c"
}
__asm__ volatile (
/* set new esp */ /* before _RAMBASE */
"movl %0, %%ebp\n\t"
"movl %0, %%esp\n\t"
::"a"( _RAMBASE - 4 )
);
{
unsigned new_cpu_reset;
/* get back cpu_reset from ebx */
__asm__ volatile (
"movl %%ebx, %0\n\t"
:"=a" (new_cpu_reset)
);
print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
if(new_cpu_reset==0) {
print_debug("done\r\n");
} else
{
print_debug("\r\n");
}
#if CONFIG_USE_INIT
printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
#else
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
/*copy and execute linuxbios_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
}
print_debug("should not be here -\r\n");
}

10
src/northbridge/amd/amdk8/coherent_ht.c
View File

@ -107,9 +107,13 @@ typedef uint32_t u32;
static inline void print_linkn (const char *strval, uint8_t byteval)
{
#if 0
#if 1
#if CONFIG_USE_INIT
printk_debug("%s%02x\r\n", strval, byteval);
#else
print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
#endif
#endif
}
static void disable_probes(void)
@ -1556,8 +1560,12 @@ static struct setup_smp_result setup_smp(void)
result = setup_smp8(result.needs_reset);
#endif
#if CONFIG_USE_INIT
printk_debug("%02x nodes initialized.\r\n", result.nodes);
#else
print_debug_hex8(result.nodes);
print_debug(" nodes initialized.\r\n");
#endif
return result;

86
src/northbridge/amd/amdk8/debug.c
View File

@ -35,21 +35,27 @@ static void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
print_debug("\r\n");
for(i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%02x:",i);
#else
print_debug("\r\n");
print_debug_hex8(i);
print_debug_char(':');
#endif
}
val = pci_read_config8(dev, i);
#if CONFIG_USE_INIT
printk_debug(" %02x", val);
#else
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
print_debug("\r\n");
}
#endif
}
print_debug("\r\n");
}
static void dump_pci_devices(void)
@ -95,50 +101,74 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel0[i];
if (device) {
int j;
#if CONFIG_USE_INIT
printk_debug("dimm: %02x.0: %02x", i, device);
#else
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".0: ");
print_debug_hex8(device);
#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%02x: ", j);
#else
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
#endif
}
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
#if CONFIG_USE_INIT
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
#endif
}
print_debug("\r\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
#if CONFIG_USE_INIT
printk_debug("dimm: %02x.1: %02x", i, device);
#else
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".1: ");
print_debug_hex8(device);
#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%02x: ", j);
#else
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
#endif
}
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
#if CONFIG_USE_INIT
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
#endif
}
print_debug("\r\n");
}
@ -151,8 +181,12 @@ static void dump_smbus_registers(void)
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
#if CONFIG_USE_INIT
printk_debug("smbus: %02x", device);
#else
print_debug("smbus: ");
print_debug_hex8(device);
#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
@ -161,13 +195,21 @@ static void dump_smbus_registers(void)
break;
}
if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%02x: ",j);
#else
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
#endif
}
byte = status & 0xff;
#if CONFIG_USE_INIT
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
#endif
}
print_debug("\r\n");
}
@ -178,21 +220,57 @@ static void dump_io_resources(unsigned port)
int i;
udelay(2000);
#if CONFIG_USE_INIT
printk_debug("%04x:\r\n", port);
#else
print_debug_hex16(port);
print_debug(":\r\n");
#endif
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_INIT
printk_debug("%02x:", i);
#else
print_debug_hex8(i);
print_debug_char(':');
#endif
}
val = inb(port);
#if CONFIG_USE_INIT
printk_debug(" %02x",val);
#else
print_debug_char(' ');
print_debug_hex8(val);
#endif
if ((i & 0x0f) == 0x0f) {
print_debug("\r\n");
}
port++;
}
}
static void dump_mem(unsigned start, unsigned end)
{
unsigned i;
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%08x:", i);
#else
print_debug("\r\n");
print_debug_hex32(i);
print_debug(":");
#endif
}
#if CONFIG_USE_INIT
printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
print_debug_hex8((unsigned char)*((unsigned char *)i));
#endif
}
print_debug("\r\n");
}
#endif

6
src/northbridge/amd/amdk8/incoherent_ht.c
View File

@ -12,9 +12,13 @@
static inline void print_linkn_in (const char *strval, uint8_t byteval)
{
#if 0
#if 1
#if CONFIG_USE_INIT
printk_debug("%s%02x\r\n", strval, byteval);
#else
print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
#endif
#endif
}
static uint8_t ht_lookup_slave_capability(device_t dev)

15
src/northbridge/amd/amdk8/raminit.c
View File

@ -31,10 +31,14 @@ static void setup_resource_map(const unsigned int *register_values, int max)
unsigned where;
unsigned long reg;
#if 0
#if CONFIG_USE_INIT
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
print_debug("\r\n");
#endif
#endif
dev = register_values[i] & ~0xff;
where = register_values[i] & 0xff;
@ -538,10 +542,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
unsigned where;
unsigned long reg;
#if 0
#if CONFIG_USE_INIT
prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
#else
print_spew_hex32(register_values[i]);
print_spew(" <-");
print_spew_hex32(register_values[i+2]);
print_spew("\r\n");
#endif
#endif
dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
where = register_values[i] & 0xff;
@ -1553,7 +1561,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
/* Update DRAM Config High with our selected memory speed */
value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
#if 1
#if 0
/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/
if(!is_cpu_pre_e0()) {
if(min_cycle_time==0x50) {
@ -2291,7 +2299,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug(" done\r\n");
}
//FIXME add enable node interleaving here --yhlu
//FIXME add enable node interleaving here -- yhlu
/*needed?
1. check how many nodes we have , if not all has ram installed get out
2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out
@ -2300,7 +2308,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node)
*/
#if CONFIG_DCACHE_RAM == 0
/* Make certain the first 1M of memory is intialized */
print_debug("Clearing initial memory region: ");
@ -2314,4 +2322,5 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
cache_lbmem(MTRR_TYPE_WRBACK);
print_debug(" done\r\n");
#endif
}

5
src/northbridge/amd/amdk8/setup_resource_map.c
View File

@ -19,6 +19,10 @@ static void setup_resource_map_x(const unsigned int *register_values, int max)
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
#if CONFIG_USE_INIT
printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
#else
print_debug_hex16(i/4);
print_debug(": ");
print_debug_hex8(register_values[i]);
@ -29,6 +33,7 @@ static void setup_resource_map_x(const unsigned int *register_values, int max)
print_debug(" | ");
print_debug_hex32(register_values[i+3]);
print_debug("\r\n");
#endif
#endif
switch (register_values[i]) {
case RES_PCI_IO: //PCI

6
src/northbridge/intel/e7501/Config.lb
View File

@ -1,7 +1,3 @@
uses CONFIG_CHIP_NAME
if CONFIG_CHIP_NAME
config chip.h
end
config chip.h
object northbridge.o

155
src/northbridge/intel/e7501/debug.c
View File

@ -17,7 +17,7 @@ static void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
@ -35,28 +35,34 @@ static void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
print_debug("\r\n");
for(i = 0; i <= 255; i++) {
for(i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%02x:",i);
#else
print_debug("\r\n");
print_debug_hex8(i);
print_debug_char(':');
#endif
}
val = pci_read_config8(dev, i);
#if CONFIG_USE_INIT
printk_debug(" %02x", val);
#else
print_debug_char(' ');
print_debug_hex8(val);
if ((i & 0x0f) == 0x0f) {
print_debug("\r\n");
}
#endif
}
print_debug("\r\n");
}
static void dump_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0, 0x1f, 0x7);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
@ -69,6 +75,23 @@ static void dump_pci_devices(void)
}
}
static void dump_pci_devices_on_bus(unsigned busn)
{
device_t dev;
for(dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
}
}
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
@ -78,87 +101,175 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel0[i];
if (device) {
int j;
#if CONFIG_USE_INIT
printk_debug("dimm: %02x.0: %02x", i, device);
#else
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".0: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%02x: ", j);
#else
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
#endif
}
status = smbus_read_byte(device, j);
if (status < 0) {
print_debug("bad device\r\n");
break;
}
byte = status & 0xff;
#if CONFIG_USE_INIT
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
#endif
}
print_debug("\r\n");
}
#if 0
device = ctrl->channel1[i];
if (device) {
int j;
#if CONFIG_USE_INIT
printk_debug("dimm: %02x.1: %02x", i, device);
#else`
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".1: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%02x: ", j);
#else
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
#endif
}
status = smbus_read_byte(device, j);
if (status < 0) {
print_debug("bad device\r\n");
break;
}
byte = status & 0xff;
#if CONFIG_USE_INIT
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
#endif
}
print_debug("\r\n");
}
#endif
}
}
static void dump_smbus_registers(void)
{
int i;
unsigned device;
print_debug("\r\n");
for(i = 1; i < 0x80; i++) {
unsigned device;
device = i;
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
#if CONFIG_USE_INIT
printk_debug("smbus: %02x", device);
#else
print_debug("smbus: ");
print_debug_hex8(device);
#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
if ((j & 0xf) == 0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%02x: ",j);
#else
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
print_debug("bad device\r\n");
break;
#endif
}
byte = status & 0xff;
#if CONFIG_USE_INIT
printk_debug("%02x ", byte);
#else
print_debug_hex8(byte);
print_debug_char(' ');
#endif
}
print_debug("\r\n");
}
}
static void dump_io_resources(unsigned port)
{
int i;
#if CONFIG_USE_INIT
printk_debug("%04x:\r\n", port);
#else
print_debug_hex16(port);
print_debug(":\r\n");
#endif
for(i=0;i<256;i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
#if CONFIG_USE_INIT
printk_debug("%02x:", i);
#else
print_debug_hex8(i);
print_debug_char(':');
#endif
}
val = inb(port);
#if CONFIG_USE_INIT
printk_debug(" %02x",val);
#else
print_debug_char(' ');
print_debug_hex8(val);
#endif
if ((i & 0x0f) == 0x0f) {
print_debug("\r\n");
}
port++;
}
}
static void dump_mem(unsigned start, unsigned end)
{
unsigned i;
print_debug("dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
#if CONFIG_USE_INIT
printk_debug("\r\n%08x:", i);
#else
print_debug("\r\n");
print_debug_hex32(i);
print_debug(":");
#endif
}
#if CONFIG_USE_INIT
printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
#else
print_debug(" ");
print_debug_hex8((unsigned char)*((unsigned char *)i));
#endif
}
print_debug("\r\n");
}
#endif

2
src/northbridge/intel/e7501/northbridge.c
View File

@ -15,6 +15,7 @@ static void pci_domain_read_resources(device_t dev)
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400; //yhlu
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
@ -187,4 +188,5 @@ static void enable_dev(struct device *dev)
struct chip_operations northbridge_intel_e7501_ops = {
CHIP_NAME("Intel E7501 northbridge")
.enable_dev = enable_dev,
};

102
src/northbridge/intel/e7501/raminit.c
View File

@ -12,7 +12,7 @@
/* converted to C 6/2004 yhlu */
#define DEBUG_RAM_CONFIG 1
#define DEBUG_RAM_CONFIG 0
#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 0))
@ -161,7 +161,7 @@ static const long register_values[] = {
* 0x2e - 0x2f
* [15:00] Subsystem ID
*/
0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
// 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16),
/* Undocumented
* 0x80 - 0x80
@ -185,6 +185,12 @@ static const long register_values[] = {
#elif CAS_LATENCY == CAS_2_0
// 0x80, 0xfffffe00, 0x0d /* values for register 0x80 */
0x80, 0xfffff000, 0x0bb1, /* values for register 0x80 */
/*
000 = HI_A Stop Grant generated after 1 Stop Grant
001 = HI_A Stop Grant generated after 2 Stop Grant
010 = HI_A Stop Grant generated after 3 Stop Grant
011 = HI_A Stop Grant generated after 4 Stop Grant*/
0x50, 0xffff1fff, 0x00006000,
#endif
/* Enable periodic memory recalibration */
@ -443,7 +449,7 @@ static const long register_values[] = {
0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0),
0xd8, 0xffff9fff, 0x00000000,
0xf4, 0x3f8ffffd, 0x40300002,
0x1050, 0xffffffcf, 0x00000030,
0x1050, 0xffffffcf, 0x00000030, // d2f0
};
@ -498,6 +504,23 @@ static void write_8dwords(uint32_t src_addr, uint32_t dst_addr) {
#define SLOW_DOWN_IO udelay(40);
#endif
/* Estimate that SLOW_DOWN_IO takes about 50&76us*/
/* delay for 200us */
#if 1
static void do_delay(void)
{
int i;
for(i = 0; i < 16; i++) { SLOW_DOWN_IO }
}
#define DO_DELAY do_delay();
#else
#define DO_DELAY \
udelay(200);
#endif
#define EXTRA_DELAY DO_DELAY
static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
uint32_t dword;
#if DEBUG_RAM_CONFIG
@ -563,7 +586,7 @@ static void ram_set_rcomp_regs(const struct mem_controller *ctrl) {
}
static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
#if DEBUG_RAM_CONFIG >= 2
#if DEBUG_RAM_CONFIG
dumpnorth();
#endif
int i;
@ -571,7 +594,7 @@ static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
max = sizeof(register_values)/sizeof(register_values[0]);
for(i = 0; i < max; i += 3) {
uint32_t reg;
#if DEBUG_RAM_CONFIG >= 2
#if DEBUG_RAM_CONFIG
print_debug_hex32(register_values[i]);
print_debug(" <-");
print_debug_hex32(register_values[i+2]);
@ -584,7 +607,7 @@ static void ram_set_d0f0_regs(const struct mem_controller *ctrl) {
}
#if DEBUG_RAM_CONFIG >= 2
#if DEBUG_RAM_CONFIG
dumpnorth();
#endif
}
@ -875,7 +898,7 @@ static long spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_
/* Test to see if I have ecc sdram */
struct dimm_page_size sz;
sz = sdram_spd_get_page_size(ctrl->channel0[i]); /* SDRAM type */
#if DEBUG_RAM_CONFIG>=2
#if DEBUG_RAM_CONFIG
print_debug("page size =");
print_debug_hex32(sz.side1);
print_debug(" ");
@ -954,6 +977,7 @@ static long spd_set_row_attributes(const struct mem_controller *ctrl, long dimm_
return dimm_mask;
}
#define spd_pre_init "Reading SPD data...\r\n"
#define spd_pre_set "setting based on SPD data...\r\n"
#define spd_post_init "done\r\n"
@ -992,17 +1016,17 @@ static long spd_set_dram_controller_mode (const struct mem_controller *ctrl, lon
/* Read the inititial state */
dword = pci_read_config32(ctrl->d0, 0x7c);
/*
// Test if ECC cmos option is enabled
#if 0
/* Test if ECC cmos option is enabled */
movb $RTC_BOOT_BYTE, %al
outb %al, $0x70
inb $0x71, %al
testb $(1<<2), %al
jnz 1f
// Clear the ecc enable
/* Clear the ecc enable */
andl $~(3 << 20), %esi
1:
*/
#endif
/* Walk through all dimms and find the interesection of the support
@ -1184,7 +1208,7 @@ static long spd_set_cas_latency(const struct mem_controller *ctrl, long dimm_mas
/* After all of the arduous calculation setup with the fastest
* cas latency I can use.
*/
value = __builtin_bsf(dword); // bsrl = log2 how about bsfl?
value = log2f(dword); // bsrl = log2 how about bsfl?
if(value ==0 ) return -1;
ecx = value -1;
@ -1348,13 +1372,13 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
unsigned dimm_mask;
int i;
dimm_mask = 0;
#if DEBUG_RAM_CONFIG
#if DEBUG_RAM_CONFIG
print_debug("spd_detect_dimms:\r\n");
#endif
for(i = 0; i < DIMM_SOCKETS; i++) {
int byte;
unsigned device;
#if DEBUG_RAM_CONFIG
#if DEBUG_RAM_CONFIG
print_debug_hex32(i);
print_debug("\r\n");
#endif
@ -1528,7 +1552,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
#if DEBUG_RAM_CONFIG
print_debug(spd_post_init);
#endif
//moved from dram_post_init
DO_DELAY
spd_set_ram_size(ctrl, dimm_mask);
return;
hw_spd_err:
@ -1539,24 +1563,6 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
}
#if 0
static void ram_postinit(const struct mem_controller *ctrl) {
#if DEBUG_RAM_CONFIG
dumpnorth();
#endif
/* Include a test to verify that memory is more or less working o.k.
* This test is to catch programming errors and hardware that is out of
* spec, not a test to see if the memory dimms are working 100%
*/
//# CALL_LABEL(verify_ram)
spd_set_ram_size(ctrl);
}
#define FIRST_NORMAL_REFERENCE() CALL_LABEL(ram_postinit)
#define SPECIAL_FINISHUP() CALL_LABEL(dram_finish)
#endif
#define ecc_pre_init "Initializing ECC state...\r\n"
#define ecc_post_init "ECC state initialized.\r\n"
static void dram_finish(const struct mem_controller *ctrl)
@ -1569,7 +1575,7 @@ static void dram_finish(const struct mem_controller *ctrl)
dword &=3;
if(dword == 2) {
#if DEBUG_RAM_CONFIG
#if DEBUG_RAM_CONFIG
print_debug(ecc_pre_init);
#endif
/* Initialize ECC bits , use ECC zero mode (new to 7501)*/
@ -1581,7 +1587,7 @@ static void dram_finish(const struct mem_controller *ctrl)
} while ( (byte & 0x08 ) == 0);
pci_write_config8(ctrl->d0, 0x52, byte & 0xfc);
#if DEBUG_RAM_CONFIG
#if DEBUG_RAM_CONFIG
print_debug(ecc_post_init);
#endif
@ -1600,7 +1606,7 @@ static void dram_finish(const struct mem_controller *ctrl)
pci_write_config32(ctrl->d0, 0x7c, dword);
#if DEBUG_RAM_CONFIG >= 2
#if DEBUG_RAM_CONFIG
dumpnorth();
#endif
@ -1621,23 +1627,6 @@ static void dram_finish(const struct mem_controller *ctrl)
#define ram_enable_11 "Ram Enable 11\r\n"
#endif
/* Estimate that SLOW_DOWN_IO takes about 50&76us*/
/* delay for 200us */
#if 1
static void do_delay(void)
{
int i;
for(i = 0; i < 16; i++) { SLOW_DOWN_IO }
}
#define DO_DELAY do_delay();
#else
#define DO_DELAY \
udelay(200);
#endif
#define EXTRA_DELAY DO_DELAY
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
@ -1737,15 +1726,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
#endif
RAM_NORMAL(ctrl);
// special from v1
//FIRST_NORMAL_REFERENCE();
//spd_set_ram_size(ctrl, 0x03);
EXTRA_DELAY
/* Finally enable refresh */
ENABLE_REFRESH(ctrl);
//SPECIAL_FINISHUP();
EXTRA_DELAY
dram_finish(ctrl);
}

7
src/pc80/Config.lb
View File

@ -1,10 +1,15 @@
uses CONFIG_IDE
uses CONFIG_LEGACY_VGABIOS
uses CONFIG_CONSOLE_VGA
object mc146818rtc.o
object isa-dma.o
object i8259.o
#object udelay_timer2.o CONFIG_UDELAY_TIMER2
#object beep.o CONFIG_BEEP
#if CONFIG_CONSOLE_VGA
# object beep.o
#end
if CONFIG_IDE
dir ide

27
src/pc80/serial.c
View File

@ -23,6 +23,9 @@
#define UART_LCS TTYS0_LCS
#if CONFIG_USE_INIT == 0
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
@ -48,14 +51,14 @@ static int uart_can_tx_byte(void)
static void uart_wait_to_tx_byte(void)
{
while(!uart_can_tx_byte())
;
while(!uart_can_tx_byte())
;
}
static void uart_wait_until_sent(void)
{
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
;
while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
;
}
static void uart_tx_byte(unsigned char data)
@ -88,3 +91,19 @@ static void uart_init(void)
#endif
outb(UART_LCS, TTYS0_BASE + UART_LCR);
}
#else
extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
static void uart_init(void)
{
#if USE_OPTION_TABLE == 1
static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
unsigned ttys0_div, ttys0_index;
ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
ttys0_index &= 7;
ttys0_div = divisor[ttys0_index];
uart8250_init(TTYS0_BASE, ttys0_div, UART_LCS);
#else
uart8250_init(TTYS0_BASE, TTYS0_DIV, UART_LCS);
#endif
}
#endif

8
src/sdram/generic_sdram.c
View File

@ -12,17 +12,25 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl)
int i;
/* Set the registers we can set once to reasonable values */
for(i = 0; i < controllers; i++) {
#if CONFIG_USE_INIT
printk_debug("Ram1.%02x\r\n",i);
#else
print_debug("Ram1.");
print_debug_hex8(i);
print_debug("\r\n");
#endif
sdram_set_registers(ctrl + i);
}
/* Now setup those things we can auto detect */
for(i = 0; i < controllers; i++) {
#if CONFIG_USE_INIT
printk_debug("Ram2.%02x\r\n",i);
#else
print_debug("Ram2.");
print_debug_hex8(i);
print_debug("\r\n");
#endif
sdram_set_spd_registers(ctrl + i);
}

19
src/southbridge/intel/i82801er/i82801er_early_smbus.c
View File

@ -46,6 +46,21 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
static int smbus_wait_until_active(void)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
do {
unsigned char val;
smbus_delay();
val = inb(SMBUS_IO_BASE + SMBHSTSTAT);
if ((val & 1)) {
break;
}
} while(--loops);
return loops?0:-4;
}
static int smbus_wait_until_ready(void)
{
unsigned long loops;
@ -113,6 +128,10 @@ static int smbus_read_byte(unsigned device, unsigned address)
/* start a byte read, with interrupts disabled */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
/* poll for it to start */
if (smbus_wait_until_active() < 0) {
return -4;
}
/* poll for transaction completion */
if (smbus_wait_until_done() < 0) {

6
targets/tyan/s2735/Config.lb
View File

@ -14,7 +14,8 @@ romimage "normal"
# 64K for Etherboot
# option ROM_SIZE = 458752
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option ROM_IMAGE_SIZE=0x11800
option XIP_ROM_SIZE=0x20000
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf
@ -28,7 +29,8 @@ end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option ROM_IMAGE_SIZE=0x11800
option XIP_ROM_SIZE=0x20000
option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
# payload ../../../payloads/tg3--ide_disk.zelf
# payload ../../../payloads/filo.elf

2
targets/tyan/s2735/VERSION
View File

@ -1 +1 @@
2.0
_s2735