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tgl mainboards: Move genx_dec settings into eSPI device scope

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Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Felix Singer
2024-06-27 23:14:31 +02:00
parent bc8f5405b5
commit 6ce6a5b369
3 changed files with 18 additions and 18 deletions
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12
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@@ -93,12 +93,6 @@ chip soc/intel/tigerlake
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
# NVMe PCIE 9 using clk 0 # NVMe PCIE 9 using clk 0
register "PcieRpLtrEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcUsage[0]" = "8"
@@ -508,6 +502,12 @@ chip soc/intel/tigerlake
end # FPMCU end # FPMCU
end end
device ref pch_espi on device ref pch_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec chip ec/google/chromeec
device pnp 0c09.0 on end device pnp 0c09.0 on end
end end

12
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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@@ -17,12 +17,6 @@ chip soc/intel/tigerlake
# CPU replacement check # CPU replacement check
register "CpuReplacementCheck" = "1" register "CpuReplacementCheck" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpSlotImplemented[8]" = "1" register "PcieRpSlotImplemented[8]" = "1"
@@ -303,6 +297,12 @@ chip soc/intel/tigerlake
end end
end end
device ref pch_espi on device ref pch_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec chip ec/google/chromeec
use conn0 as mux_conn[0] use conn0 as mux_conn[0]
use conn1 as mux_conn[1] use conn1 as mux_conn[1]

12
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@@ -17,12 +17,6 @@ chip soc/intel/tigerlake
# CPU replacement check # CPU replacement check
register "CpuReplacementCheck" = "1" register "CpuReplacementCheck" = "1"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "PcieRpSlotImplemented[2]" = "1" register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpSlotImplemented[3]" = "1" register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpSlotImplemented[8]" = "1" register "PcieRpSlotImplemented[8]" = "1"
@@ -308,6 +302,12 @@ chip soc/intel/tigerlake
end end
end end
device ref pch_espi on device ref pch_espi on
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
chip ec/google/chromeec chip ec/google/chromeec
use conn0 as mux_conn[0] use conn0 as mux_conn[0]
use conn1 as mux_conn[1] use conn1 as mux_conn[1]