armv7: specify condition code for msr instruction

This adds condition codes when using the msr instruction. Although
described as "optional" in the Cortex-A series programmer's guide,
our experience with using the msr instruction in the payload suggests
that the condition code is not optional and that this only worked
in coreboot (and u-boot) because the processor comes up in SVC32 mode.

(credit to Gabe Black for finding this, I'm only uploading the patch)

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I0aa4715ae415e1ccc5719b7b55adcd527cc1597b
Reviewed-on: http://review.coreboot.org/3037
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

This commit is contained in:

David Hendricks

2013-04-07 17:26:34 -07:00

committed by

Ronald G. Minnich

parent c7e5d79842

commit 6d0fe9cad0

1 changed files with 1 additions and 1 deletions

									
										2

src/arch/armv7/bootblock.inc
									
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				@@ -58,7 +58,7 @@ reset:

					mrs	r0, cpsr

					bic	r0, r0, #0x1f

					orr	r0, r0, #0xd3

					msr	cpsr,r0

					msr	cpsr_cxsf,r0

					/*

					 * From Cortex-A Series Programmer's Guide:

armv7: specify condition code for msr instruction

2 src/arch/armv7/bootblock.inc Unescape Escape View File

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src/arch/armv7/bootblock.inc

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