diff --git a/src/mainboard/system76/galp5/Kconfig b/src/mainboard/system76/galp5/Kconfig
index 8c97a143a4..8758e7f347 100644
--- a/src/mainboard/system76/galp5/Kconfig
+++ b/src/mainboard/system76/galp5/Kconfig
@@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_16384
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
+	select DRIVERS_INTEL_USB4_RETIMER
 	select DRIVERS_SYSTEM76_DGPU
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
@@ -23,7 +24,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_RDRESP_NEED_DELAY
-	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/system76/galp5/acpi/mainboard.asl b/src/mainboard/system76/galp5/acpi/mainboard.asl
index 2d3b4b63c5..c982a9ee4c 100644
--- a/src/mainboard/system76/galp5/acpi/mainboard.asl
+++ b/src/mainboard/system76/galp5/acpi/mainboard.asl
@@ -1,10 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/*TODO: TGL-U not yet supported
-#include "../gpio.h"
-#include <drivers/system76/dgpu/acpi/dgpu.asl>
-*/
-
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
diff --git a/src/mainboard/system76/galp5/acpi/sleep.asl b/src/mainboard/system76/galp5/acpi/sleep.asl
index 46392550b8..48c50e075e 100644
--- a/src/mainboard/system76/galp5/acpi/sleep.asl
+++ b/src/mainboard/system76/galp5/acpi/sleep.asl
@@ -3,11 +3,6 @@
 /* Method called from _PTS prior to enter sleep state */
 Method (MPTS, 1) {
 	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
-
-/*TODO: TGL-U not yet supported 
-	// Turn DGPU on before sleeping
-	\_SB.PCI0.PEGP.DEV0._ON()
-*/
 }
 
 /* Method called from _WAK prior to wakeup */
diff --git a/src/mainboard/system76/galp5/devicetree.cb b/src/mainboard/system76/galp5/devicetree.cb
index 0f269367cb..eaec88b6d3 100644
--- a/src/mainboard/system76/galp5/devicetree.cb
+++ b/src/mainboard/system76/galp5/devicetree.cb
@@ -79,9 +79,52 @@ chip soc/intel/tigerlake
 	# Enable DPTF device
 	register "Device4Enable" = "1"
 
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
 	#TODO: Hybrid storage mode
 	register "HybridStorageMode" = "0"
 
+	# Default IOM Port Config
+	register "IomTypeCPortPadCfg[0]" = "0x09000000"
+	register "IomTypeCPortPadCfg[1]" = "0x09000000"
+	register "IomTypeCPortPadCfg[2]" = "0x09000000"
+	register "IomTypeCPortPadCfg[3]" = "0x09000000"
+	register "IomTypeCPortPadCfg[4]" = "0x09000000"
+	register "IomTypeCPortPadCfg[5]" = "0x09000000"
+	register "IomTypeCPortPadCfg[6]" = "0x09000000"
+	register "IomTypeCPortPadCfg[7]" = "0x09000000"
+
+	# Read LPM_EN, make sure to invert the bits
+	# sudo devmem2 0xfe001c78
+	# 0x9
+	register "LpmStateDisableMask" = "
+		LPM_S0i2_1 |
+		LPM_S0i2_2 |
+		LPM_S0i3_1 |
+		LPM_S0i3_2 |
+		LPM_S0i3_3 |
+		LPM_S0i3_4
+	"
+
 	# I2C channels
 	register "SerialIoI2cMode" = "{
 		[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
@@ -187,6 +230,7 @@ chip soc/intel/tigerlake
 # PM Util (soc/intel/tigerlake/pmutil.c)
 	# GPE configuration
 	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	# 0x432
 	register "pmc_gpe0_dw0" = "PMC_GPP_A"
 	register "pmc_gpe0_dw1" = "PMC_GPP_R"
 	register "pmc_gpe0_dw2" = "PMC_GPD"
@@ -207,17 +251,30 @@ chip soc/intel/tigerlake
 		device pci 02.0 on  end # Graphics
 		device pci 04.0 on  end # DPTF			0x9A03
 		device pci 05.0 off end # IPU			0x9A19
-		device pci 06.0 on  end # PEG60			0x9A09
+		device pci 06.0 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
+				#TODO: Support disable/enable CPU RP clock
+				register "srcclk_pin" = "-1" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
+		end # PEG60			0x9A09
 		device pci 07.0 on  end # TBT_PCIe0		0x9A23
 		device pci 07.1 off end # TBT_PCIe1		0x9A25
 		device pci 07.2 off end # TBT_PCIe2		0x9A27
 		device pci 07.3 off end # TBT_PCIe3		0x9A29
-		device pci 08.0 off end # GNA			0x9A11
+		device pci 08.0 on  end # GNA			0x9A11
 		device pci 09.0 off end # NPK			0x9A33
 		device pci 0a.0 on  end # Crash-log SRAM	0x9A0D
 		device pci 0d.0 on  end # USB xHCI		0x9A13
 		device pci 0d.1 off end # USB xDCI (OTG)	0x9A15
-		device pci 0d.2 on  end # TBT DMA0		0x9A1B
+		device pci 0d.2 on
+			chip drivers/intel/usb4/retimer
+				register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
+				device generic 0 on end
+			end
+		end # TBT DMA0		0x9A1B
 		device pci 0d.3 off end # TBT DMA1		0x9A1D
 		device pci 0e.0 off end # VMD			0x9A0B
 
@@ -265,12 +322,27 @@ chip soc/intel/tigerlake
 		device pci 1c.1 off end # RP2			0xA0B9
 		device pci 1c.2 off end # RP3			0xA0BA
 		device pci 1c.3 off end # RP4			0xA0BB
-		device pci 1c.4 on  end # RP5			0xA0BC
+		device pci 1c.4 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH
+				register "srcclk_pin" = "2" # PEG_CLKREQ#
+				device generic 0 on end
+			end
+		end # RP5			0xA0BC
 		device pci 1c.5 off end # RP6			0xA0BD
 		device pci 1c.6 off end # RP7			0xA0BE
 		device pci 1c.7 off end # RP8			0xA0BF
 		device pci 1d.0 on  end # RP9			0xA0B0
-		device pci 1d.1 on  end # RP10			0xA0B1
+		device pci 1d.1 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN
+				#TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ?
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # GPIO_LANRTD3
+				register "srcclk_pin" = "4" # LAN_CLKREQ#
+				device generic 0 on end
+			end
+		end # RP10			0xA0B1
 		device pci 1d.2 on  end # RP11			0xA0B2
 		device pci 1d.3 off end # RP12			0xA0B3
 		device pci 1e.0 off end # UART0			0xA0A8
diff --git a/src/mainboard/system76/galp5/dsdt.asl b/src/mainboard/system76/galp5/dsdt.asl
index 5983937cf6..e77f70bd65 100644
--- a/src/mainboard/system76/galp5/dsdt.asl
+++ b/src/mainboard/system76/galp5/dsdt.asl
@@ -4,30 +4,38 @@
 #define SYSTEM76_ACPI_NO_GFX0
 
 #include <acpi/acpi.h>
+
 DefinitionBlock(
 	"dsdt.aml",
 	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
+	ACPI_DSDT_REV_2,
 	OEM_ID,
 	ACPI_TABLE_CREATOR,
 	0x20110725	// OEM revision
 )
 {
 	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	// global NVS and variables
 	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	// CPU
 	#include <cpu/intel/common/acpi/cpu.asl>
 
-	Device (\_SB.PCI0) {
-		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
-		#include <soc/intel/tigerlake/acpi/southbridge.asl>
-		#include <soc/intel/tigerlake/acpi/tcss.asl>
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+			#include <soc/intel/tigerlake/acpi/southbridge.asl>
+			#include <soc/intel/tigerlake/acpi/tcss.asl>
+		}
 	}
 
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
 	Scope (\_SB.PCI0.LPCB) {
 		#include <drivers/pc80/pc/ps2_controller.asl>
 	}
 
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
 	#include "acpi/mainboard.asl"
 }
diff --git a/src/mainboard/system76/lemp10/devicetree.cb b/src/mainboard/system76/lemp10/devicetree.cb
index 39ac541310..e24bae9e23 100644
--- a/src/mainboard/system76/lemp10/devicetree.cb
+++ b/src/mainboard/system76/lemp10/devicetree.cb
@@ -228,6 +228,7 @@ chip soc/intel/tigerlake
 # PM Util (soc/intel/tigerlake/pmutil.c)
 	# GPE configuration
 	# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+	# TODO: 0x703
 	register "pmc_gpe0_dw0" = "PMC_GPP_R"
 	register "pmc_gpe0_dw1" = "PMC_GPP_B"
 	register "pmc_gpe0_dw2" = "PMC_GPP_D"