From 6d20bf4a9f31b00dbfc61d68038103de003f850b Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Thu, 26 May 2022 09:02:13 -0600 Subject: [PATCH] soc/intel/alderlake: Add SLP_S0 residency register and enable LPIT support Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413 --- src/soc/intel/alderlake/Kconfig | 1 + src/soc/intel/alderlake/include/soc/pmc.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 76bcbf9a7c..5a6ac7f9c2 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -74,6 +74,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index d1e63bc5cf..5caa71afff 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -136,6 +136,8 @@ extern struct device_operations pmc_ops; #define HPR_CAUSE0_MI_HRPC (1 << 9) #define HPR_CAUSE0_MI_HR (1 << 8) +#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22)