sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/tigerlake: Move PMC PCI resources under PMC device

Browse Source 
Historically in coreboot, the PMC's fixed PCI resources were described
by the System Agent (the MMIO resource), and eSPI/LPC (the I/O
resource). This patch moves both of those to a new Intel SoC-specific
function, soc_pmc_read_resources(). On TGL, this new function takes care
of providing the MMIO and I/O resources for the PMC.

BUG=b:156388055
TEST=verified on volteer that the resource allocator is aware of and
does not touch these two resources:
("PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0
	flags f0000200 index 0
  PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff
	flags c0000100 index 1")

Also verify that the MEM resource is described in the coreboot table:
("BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved")

Verified the memory range is also untouchable from Linux:
("system 00:00: [mem 0xfe000000-0xffffffff] could not be reserved")

Change-Id: Ia7c6ae849aefaf549fb682416a87320907fb3fe3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41385
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak
2020-05-13 17:00:33 -06:00
committed by Patrick Georgi
parent dbcf7b1621
commit 6d20d0c140
9 changed files with 42 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@@ -243,7 +243,7 @@ chip soc/intel/tigerlake
device pci 1e.3 off end # GSPI1 0xA0AB
device pci 1f.0 on end # eSPI 0xA080 - A09F
device pci 1f.1 on end # P2SB 0xA0A0
device pci 1f.2 on end # PMC 0xA0A1
device pci 1f.2 hidden end # PMC 0xA0A1
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
device pci 1f.4 on end # SMBus 0xA0A3
device pci 1f.5 on end # SPI 0xA0A4

2
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@@ -239,7 +239,7 @@ chip soc/intel/tigerlake
device pci 1e.3 off end # GSPI1 0xA0AB
device pci 1f.0 on end # eSPI 0xA080 - A09F
device pci 1f.1 on end # P2SB 0xA0A0
device pci 1f.2 on end # PMC 0xA0A1
device pci 1f.2 hidden end # PMC 0xA0A1
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
device pci 1f.4 on end # SMBus 0xA0A3
device pci 1f.5 on end # SPI 0xA0A4